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HDMI接口编解码传输模块ASIC设计_刘文杰
? 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
? 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。
? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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COSTAS_LOOP
用verilog编写的科斯塔斯环，希望有帮助(Costas loop written in verilog helpful)
- 2012-10-31 23:01:23下载
- 积分：1
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fft
FPGA实现FFT算法的源代码及工程文件，此工程为ISE工程项目。有详细的说明，可以运行。(FPGA Implementation of FFT algorithm source code and project files, this works for the ISE project. There are detailed instructions, you can run.)
- 2013-10-12 17:21:32下载
- 积分：1
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Gap_Finder
this example finds the gapes that are existed in a word
- 2010-01-29 18:41:25下载
- 积分：1
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Using VHDL programming asynchronous FIFO procedure can be run by the debugger
使用VHDL编程的异步FIFO程序 经调试可运行-Using VHDL programming asynchronous FIFO procedure can be run by the debugger
- 2022-03-23 14:37:37下载
- 积分：1
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vhdl code for multiplexer and detemines how multiplexer works
vhdl code for multiplexer and detemines how multiplexer works
- 2022-02-21 06:20:43下载
- 积分：1
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VHDL basic arithmetic library, a very handy! !
VHDL的基本数学运算库,非常好用-VHDL basic arithmetic library, a very handy! !
- 2023-01-24 20:00:03下载
- 积分：1
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verilog
《数字信号处理的FPGA实现（第三版）》作者：U.Meyer-Baese
的配套源码，基于quartus9.0编写，使用的cyclone ii。其中包含FIR IIR FFT等算法的实现，对学习图像处理很有帮助。( FPGA digital signal processing (third edition) Author: U.Meyer-Baese
The matching source, based on quartus9.0 preparation, the use of cyclone ii. Which includes FIR IIR FFT algorithm such as the realization of learning to image processing helpful.)
- 2016-12-21 10:14:26下载
- 积分：1
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counter4b
Vivado同步计数器VHDL设计 具有异步复位和同步预置数功能 同步计数器同步计数器同步计数器(The Vivado synchronous counter VHDL is designed with asynchronous reset and synchronous preset function, synchronous counter, synchronous counter and synchronous counter.)
- 2021-03-26 14:29:13下载
- 积分：1
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基于单片机与CPLD的 等精度频率计，VHDL语言
基于单片机与CPLD的 等精度频率计，VHDL语言-Based on SCM and CPLD
- 2022-11-25 20:35:03下载
- 积分：1
