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vhdl testbench的编写,textio的编写是一个难点,也是一个重点,而这是本人搜集的多篇关于textio的文章,同时附有简单注释!...
vhdl testbench的编写,textio的编写是一个难点,也是一个重点,而这是本人搜集的多篇关于textio的文章,同时附有简单注释!-vhdl testbench preparation, textio the preparation is a difficult, but also a focus, and this is my collection of articles on textio the article, at the same time with a simple note!
- 2022-10-01 22:10:03下载
- 积分:1
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tpc_vhd
完整的TPC编译码VHDL程序,直接就可以运行(TPC encoder and decoder)
- 2020-11-21 15:29:36下载
- 积分:1
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任意基数分频VERILOG代码,经过了编译,可以修改数字改变分频。...
任意基数分频VERILOG代码,经过了编译,可以修改数字改变分频。-Arbitrary base frequency Verilog code, after compilation, the figures can be amended to change the frequency.
- 2022-08-10 12:37:41下载
- 积分:1
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这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!...
这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!-This is my learning process in the middle of the 10-minute program, containing various clock module and the counter, accumulator, and can download, compile!
- 2022-07-19 00:32:21下载
- 积分:1
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本文介绍了汉明编码与译码通过FPGA器件来实现,介绍了使用VHDL语言编程的基本算法!...
本文介绍了汉明编码与译码通过FPGA器件来实现,介绍了使用VHDL语言编程的基本算法!-This article describes the Hamming encoding and decoding through the FPGA device to implement, introduced the use of VHDL programming language is the basic algorithm!
- 2022-01-28 18:13:46下载
- 积分:1
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4x4-Keypad
fpga的一个小程序用于3s500e 4*4键盘模块(fpga is a small program used 3s500e 4* 4 keyboard module)
- 2013-07-21 11:41:36下载
- 积分:1
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EDA设计实验,用VHDL编写的数字时钟代码,能显示分,秒,小时。根据所设置的频率不同,能够调整时间快慢。...
EDA设计实验,用VHDL编写的数字时钟代码,能显示分,秒,小时。根据所设置的频率不同,能够调整时间快慢。-EDA design of experiments, prepared by VHDL code digital clock showing the hours, seconds, hours. According to the frequency of different settings, time to adjust speed.
- 2022-10-28 17:25:03下载
- 积分:1
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FPGA开发全攻略
FPGA设计攻略及流程,包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)
- 2017-12-12 16:30:52下载
- 积分:1
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数字计时器,使用VHDL语言编写,使用数码管显示,精确到ms
数字计时器,使用VHDL语言编写,使用数码管显示,精确到ms-digital timer, the use of VHDL development, the use of digital control, the precision of the ms
- 2022-05-20 00:23:22下载
- 积分:1
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sobel
这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件,可在QuartusII或MaxplisII下综合和仿真,并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测,同时还可以实现其它的图像模块化处理算法,例如高斯滤波,平滑等。(this is my own preparation for the 256* 256 size of the image segmentation Edge Detection vhd document in the next QuartusII or MaxplisII integrated and simulation, and the FPGA tested. Can be adapted to support other size image segmentation edge detection, It can also achieve other modular image processing algorithms, such as Gaussian filtering, smoothing and so on.)
- 2020-07-09 21:08:55下载
- 积分:1