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SoC_WishboneSystem
SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)
- 2008-01-03 11:14:59下载
- 积分：1
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FPGA
基于FPGA的多功能波形发生器,很好的,使用Verilong程序。(FPGA-based multi-function waveform generator, a good use of Verilong program.)
- 2011-05-20 18:23:40下载
- 积分：1
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tb_time_offfset
说明： offset_cancellation code for matlab to hdl
- 2020-06-17 12:20:02下载
- 积分：1
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digital_clock
说明： 数字钟通过verilog实现，并且支持Modelsim仿真，通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)
- 2020-06-18 05:00:02下载
- 积分：1
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dianziqingsheji
实现拟想要的音乐，基于at89s51单片机的电子琴设计！(To achieve the desired music to be based at89s51 keyboard microcontroller design!)
- 2010-05-19 14:01:34下载
- 积分：1
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the major digital TV front
主要完成数字电视前端信号处理和缓冲作用的verilog源代码，可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
- 2022-04-09 13:15:30下载
- 积分：1
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VGA
verilog vga 图像处理(verilog vga)
- 2013-10-15 19:00:16下载
- 积分：1
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本文介绍了汉明编码与译码通过FPGA器件来实现，介绍了使用VHDL语言编程的基本算法！...
本文介绍了汉明编码与译码通过FPGA器件来实现，介绍了使用VHDL语言编程的基本算法！-This article describes the Hamming encoding and decoding through the FPGA device to implement, introduced the use of VHDL programming language is the basic algorithm!
- 2022-01-28 18:13:46下载
- 积分：1
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DI-S-AND-V
这个程序是为了区分SIGNAL和VARIABLE在不同情况下要怎样使用的例程，程序中使用了三种情况来说明问题(This program is designed to differentiate between routine SIGNAL VARIABLE in different situations and how you want to use, the program uses the three cases to illustrate the problem
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- 2015-01-12 12:56:26下载
- 积分：1
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dualportram_vhdl
采用VHDL硬件描述语言实现的双口径RAM块存储器的初始化(VHDL hardware description language using the dual-caliber RAM block memory initialization)
- 2010-06-17 10:22:47下载
- 积分：1
