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CSCC标准下的RS码译码器的FPGA实现

于 2022-03-24 发布 文件大小:12.12 MB
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代码说明:

CSCC标准下的RS(255,223)码的译码器设计,采用verilog语言编程实现,在软件QUARTUS II 9.0环境下仿真通过,并在CYCLONE IV系列开发板调试通过。

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