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hdb3_codedecode
说明： 用VERILOG实现的，hdb3编码器和解码器，经过前仿真和后仿真成功(Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation)
- 2021-04-22 15:58:49下载
- 积分：1
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vivado2017+下的HDMI环路视频代码（AX7103）
在黑金AX7103板子上（A7）实现的demo工程中，存在一些bug。给与修正
- 2022-05-12 17:34:33下载
- 积分：1
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axi_spi_master
arm的axi接口转spi接口master源代码，已经使用过，带注释，
- 2022-03-23 04:14:36下载
- 积分：1
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widgets
CSS配合jquery制作完美漂亮的时钟，貌似在IE8下时钟不能获取时间啊！支持ie9、chrome、safari、firefox、opera （Chrome显示效果最佳，IE9下时钟无法工作）日历和骰子是原创，CSS3时钟并非原创但经过改良支持opera。数字日历的兼容性不错，圆形时钟就差点了，也希望一起交流，共同改进。(CSS with the jquery make perfect beautiful clock, seemingly in IE8 under the clock can not get the time ah! Support ie9, chrome, safari, firefox, opera (Chrome show the best results, the clock does not work under IE9) calendar and dice is original, CSS3 clock is not original but after improved support opera. Digital calendar compatibility is good, almost round the clock on, and also hope together, and work together to improve.)
- 2014-10-31 09:25:37下载
- 积分：1
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serial_communication
说明： 串口操作源代码，本代码采用veilog hdl语言编写，并经过本人多次验证。(source code, the code used veilog HDL language, and after I repeatedly verified.)
- 2006-04-06 09:38:19下载
- 积分：1
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Verilog LED 斯巴达 6
此代码是 verilog 代码和斯巴达 6 模型规范代码。欢迎大家下载、试用。谢谢大家的支持。
- 2022-03-01 23:14:35下载
- 积分：1
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PCPU设计代码
说明： RISC 5级流水线CPU，带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)
- 2020-06-24 04:00:01下载
- 积分：1
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vhdl1008
说明： PCI slave IP core, in VHDL language ,has been verified,it is very easy to use.
it is an ideal IP to study PCI,design PCI Bridge
- 2020-06-18 18:20:01下载
- 积分：1
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UART module Verilog codes and guidance
Verilog codes of UART modules and guidances of UART
- 2022-05-19 07:09:53下载
- 积分：1
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syn
载波同步的verilog代码，是新手学习同步的最佳选择，值得推荐。(Verilog code carrier synchronization, synchronization is the best choice for novices to learn, it is worth recommending.)
- 2021-01-08 09:48:51下载
- 积分：1
