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是用于pci开发的核,可以将硬件的信息映射到然间上来 节省出开发人员用于了解硬件的时间...
是用于pci开发的核,可以将硬件的信息映射到然间上来 节省出开发人员用于了解硬件的时间 -Pci developed for nuclear, hardware information can be mapped to the inter-ran up to save the developers time to understand the hardware
- 2022-01-26 02:12:56下载
- 积分:1
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com1027soft
FSK/MSK/GFSK/GMSK
DIGITAL DEMODULATOR
VHDL SOURCE CODE OVERVIEW
- 2011-03-21 22:41:15下载
- 积分:1
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数字点阵赛车
数字电路点阵赛车,分为开始前5秒倒计时,59秒计时,赛车显示,赛道显示,失败提示,成功提示,移动控制以及总控制等8个模块。实现由3个开关控制点阵赛车在设置好的赛道中前进或左右移动。
- 2022-04-10 09:21:03下载
- 积分:1
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This is a simple routine FPGA is mainly based on FPGA
这是一个FPGA的简单例程,主要是基于FPGA的232串口通信的例程-This is a simple routine FPGA is mainly based on FPGA-232 serial communication routines
- 2022-03-06 20:54:43下载
- 积分:1
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median
说明: 用verilog编辑的中值滤波器!语言旁表有注释方便理解!(Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!)
- 2008-11-03 09:21:18下载
- 积分:1
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8051corelcd
fpga上实现的51内核,带有LCD试验,顺利试验成功很好用。(on fpga implementation of 51 core with LCD test, successfully tested well with the smooth.)
- 2014-03-30 14:35:20下载
- 积分:1
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60进制减法
相比较 代码效率高
可以进行级联
60进制减法
相比较 代码效率高
可以进行级联-60 compared to 229 subtraction efficient code can be concatenated
- 2022-01-25 18:25:04下载
- 积分:1
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fir_lms
基于FPGA的自适应滤波器的实现。采用Verilog编程,2阶滤波器。(FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.)
- 2009-04-27 12:06:25下载
- 积分:1
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ps2接口源程序。标准的键盘和鼠标接口,在Xilinx SpartanII XC2S200 实验板上通过验证...
ps2接口源程序。标准的键盘和鼠标接口,在Xilinx SpartanII XC2S200 实验板上通过验证-ps2 interface source. Standard keyboard and mouse interface, in the experiments on-board Xilinx SpartanII XC2S200 validated
- 2023-03-24 22:15:03下载
- 积分:1
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described dds direct digital frequency synthesis of the basic tenets addition to...
讲述了dds直接数字频率合成的基本原理,同时用VHDL语言编写dds原代码用于生成正弦波,并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output
- 2022-07-08 20:48:31下载
- 积分:1