登录
首页 » VHDL » 步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过

步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过

于 2022-04-25 发布 文件大小:1.41 MB
0 129
下载积分: 2 下载次数: 1

代码说明:

步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过-Stepper motor stepper motor position location system system block symbol file location stepper motor system Verilog HDL program design has been compiled through

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 由于在网上很难下载到EDA技术-窦衡的PPT,所以本人经过学习后做成word,供大家下载。只针对VHDL语言部分和所有的程序。...
    由于在网上很难下载到EDA技术-窦衡的PPT,所以本人经过学习后做成word,供大家下载。只针对VHDL语言部分和所有的程序。-Because the Internet is difficult to download to EDA technology- Douheng of the PPT, so I made after learning after the word, for all to download. Only for part of the VHDL language and all the procedures.
    2023-07-12 15:25:04下载
    积分:1
  • crc16_8
    modbus通讯必须的校验码生成器,可以直接使用(modbus crc16/8 free use)
    2020-10-22 10:47:23下载
    积分:1
  • adda
    说明:  基于FPGA 黑金ALINX 515的 ADDA采样模块源码(需调试)(ADDA Sampling Module Source Code Based on FPGA Heijin ALINX 515)
    2020-06-20 13:00:01下载
    积分:1
  • verilog实现基于i2s协议接口 i2s_interface
    verilog实现基于i2s协议接口,在fpga上验证通过。(Verilog implements the interface based on I2S protocol and verifies it on fpga.)
    2017-11-05 17:26:39下载
    积分:1
  • pl_read_write_ps_ddr
    说明:  PL 和 PS 的高效交互是 zynq 7000 soc 开发的重中之重,常常需要将 PL 端的大量数据实时送到 PS 端处理,或者将 PS 端处理结果实时送到 PL 端处理,但是各种协议非常麻烦,灵活性也比较差,直接通过 AXI 总线来读写 PS 端 ddr 的数据,这里面涉及到 AXI4 协议,vivado 的 FPGA 调试等。(The efficient interaction between PL and PS is the top priority of zynq 7000 SoC development. We often need to send a large amount of data from PL to PS for real-time processing, or send the processing results from PS to pl for real-time processing. In general, we will think of using DMA for processing, but various protocols are very troublesome and the flexibility is poor. This course explains how to use Axi directly Bus to read and write DDR data of PS terminal, which involves axi4 protocol, FPGA debugging of vivado, etc.)
    2021-01-22 17:46:44下载
    积分:1
  • FM radio decoder and controller VHDL, Xilinx provide. I thank other.
    FM收音机的解码及控制器VHDL语言实现,Xilinx提供的.别谢我.-FM radio decoder and controller VHDL, Xilinx provide. I thank other.
    2022-10-05 04:50:03下载
    积分:1
  • Documentation Of Digital Electronic Systems With VHDL from US DOD.
    Documentation Of Digital Electronic Systems With VHDL from US DOD.
    2022-05-09 12:50:24下载
    积分:1
  • min_max_finder_part1
    最大最小值寻找程序,可以实现自动查找最大值与最小值(min_max_finder)
    2010-09-25 01:19:09下载
    积分:1
  • 基于FPGA的CPU核及其虚拟平台的设计与实现
    基于FPGA的CPU核及其虚拟平台的设计与实现-FPGA-based CPU core and its virtual platform design and implementation of
    2022-08-08 02:35:45下载
    积分:1
  • 3P3_wimdow
    图像插值算法,窗口为3*3,用于图像的除去死点,以及提高清晰度或者使图像柔和(3*3 window)
    2012-02-28 15:36:02下载
    积分:1
  • 696518资源总数
  • 105895会员总数
  • 18今日下载