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一个用VHDL完成的8位数显的16进制的频率计
一个用VHDL完成的8位数显的16进制的频率计-a VHDL completed 8 of 16 significant median band of frequency meter
- 2022-01-31 16:47:07下载
- 积分：1
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ps2interface
one of example about hardware design language
- 2009-12-25 07:17:18下载
- 积分：1
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bundle_test5
说明： 一个具备bp协议典型功能的数据传输系统（超时重传机制以及托管传输）包含五个节点(A data transmission system with typical functions of BP protocol (Overtime retransmission mechanism and managed transmission) consists of five nodes)
- 2019-12-02 19:06:44下载
- 积分：1
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LMS filter
这是一个用结构化语言编写的25抽头LMS算法建模.VHDL加法器/减法器、乘法器、延迟元件的代码分别编写并用LMS代码实例化。
- 2022-02-10 10:42:31下载
- 积分：1
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FPGA应用举例，非常适合初学者，高手莫下
FPGA应用举例，非常适合初学者，高手莫下-FPGA application, for example, very suitable for beginners, experts, under Mo
- 2022-10-06 03:30:03下载
- 积分：1
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SystemVerilog_For_Design_Springer_2nd_Ed_2006
SystemVerilog For Design (Springer-2nd_Ed-2006)
- 2009-10-08 02:57:28下载
- 积分：1
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wbm
用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.(algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.)
- 2006-07-12 14:49:35下载
- 积分：1
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一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。...
一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
- 2023-06-07 08:05:03下载
- 积分：1
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通用：我新的FFT VHDL VHDL，我试图用Xilinx的FFT核，但当…
FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity o
- 2022-06-20 20:06:05下载
- 积分：1
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RS_DesignNote
Reed-solomon decoder, encoder design note
- 2010-08-16 09:16:04下载
- 积分：1
