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pipeline_FPGA
FPGA流水线设计的资料，可以作为学习FPGA开发并行操作的一个经典教材，具有很好的指导作用。(FPGA pipeline design information can be developed as a learning FPGA parallel operation of a classic textbook, has a good guide.)
- 2011-07-02 12:00:57下载
- 积分：1
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vga编程。实现3种模式的vga控制，分别产生横彩条，竖彩条，棋格彩条的显示...
vga编程。实现3种模式的vga控制，分别产生横彩条，竖彩条，棋格彩条的显示-vga programming. Realization of the three-mode vga control, generate horizontal color of the color of the shaft, and the chess grid color of the show
- 2023-04-18 23:15:03下载
- 积分：1
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EP2C70F896C6N-pins
将VHDL程序下载到DE2开发板，引脚分配时需要知道的芯片每个引脚功能(VHDL program will be downloaded to the DE2 development board, you need to know when the pin assignments for each pin of the chip functions)
- 2020-12-09 11:09:21下载
- 积分：1
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Verilog代码。注册成功，对FPGA的使用标准单元库…
verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
- 2022-01-31 00:50:36下载
- 积分：1
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RS(204-188)decoder_verilog
采用verilog实现的有限域GF(28)弱对偶基乘法器，本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ，多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7}，弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}(Verilog achieved using the finite field GF (28) weak dual basis multiplier)
- 2016-06-12 16:31:51下载
- 积分：1
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C51tou-wen-jian
是51单片机常用头文件定义，直接调用就可以，包括：1602液晶，12864液晶，5110屏，I2C,UART,精确延时函数，PWM调速，DS1302，DS18B20,,,,,,,(51 microcontroller used header file defines direct call can include: 1602 LCD, 12864 LCD, 5110 screen, I2C, UART, precision delay function PWM speed control, DS1302, DS18B20,,,,,)
- 2013-04-15 17:34:22下载
- 积分：1
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子字节的有效执行
应用背景此文件包括执行与数学计算的子字节。查找表和组合方法已被包括在内。关键技术Xilinx XC3S400 VHDL编程语言已经使用这些代码。
- 2023-05-26 21:50:03下载
- 积分：1
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加法计数器的VHDL工程，程序，仿真图形
加法计数器的VHDL工程，程序，仿真图形-adder jishuqi de VHDL FANGZHEN ,CHENGXU
- 2022-01-25 14:28:29下载
- 积分：1
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VHDL language design stopwatch, timer function of the realization, the realizati...
VHDL语言设计的秒表，实现计时功能，实现报时功能，并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.
- 2022-09-16 02:55:02下载
- 积分：1
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myuart
使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路(Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas)
- 2013-07-25 11:45:57下载
- 积分：1
