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一些简单的VHDL实例,主要是介绍一些基本逻辑们及一些组合、时序电路的例子,供大家参考...
一些简单的VHDL实例,主要是介绍一些基本逻辑们及一些组合、时序电路的例子,供大家参考-Some simple examples of VHDL, mainly to introduce some basic logic and some combination of sequential circuit examples for your reference
- 2022-01-31 04:35:55下载
- 积分:1
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出租车模块设计加nios2设计cup程序代码
出租车模块设计加nios2设计cup程序代码...
出租车模块设计加nios2设计cup程序代码
出租车模块设计加nios2设计cup程序代码-Taxi modular design design cup plus nios2 code taxi modular design design cup plus nios2 code
- 2022-03-06 17:30:37下载
- 积分:1
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raylrnb (3)
说明: 本资源有一个matlab程序段,是仿真BPSK分别在高斯噪声和瑞利衰落下的误码率,产生图形对仿真值和理论值进行比较(This resource has a matlab program segment, which is the bit error rate of simulated BPSK under Gaussian noise and Rayleigh fading respectively. The generated graph compares the simulated value with the theoretical value.)
- 2019-10-21 21:16:04下载
- 积分:1
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hdlc
HDLC通信协议,FPGA实现,包含源文件和仿真测试文件。(HDLC comunication)
- 2014-08-28 21:37:31下载
- 积分:1
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开发系统上采用的时钟信号的频率是20MHz,可分别设计计数器对其计数,包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出,这样就构成了一个电子日历和时钟...
开发系统上采用的时钟信号的频率是20MHz,可分别设计计数器对其计数,包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出,这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值,还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit
- 2022-08-07 06:47:58下载
- 积分:1
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在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意...
在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意-QuartusII warning solving
- 2022-03-01 12:03:29下载
- 积分:1
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I2C
K2FPGA开发板实验教程——I2C协议说明及verilog实现读写I2C器件,中文内涵代码,验证可用。(K2FPGA development board test tutorial- I2C protocol description and verilog read and write I2C devices, Chinese connotation code to verify availability.)
- 2014-03-28 16:37:59下载
- 积分:1
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VGA FPGA时序仿真,仿真的PS / 2键盘接口VHDL源C.
用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码,基于Xilinx spartan3-VGA FPGA timing simulation, simulation PS/2 keyboard interface bus VHDL source code, Based on Xilinx spartan3
- 2023-01-19 01:15:04下载
- 积分:1
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俩个比较好的计数器的vhdl代码:一个是n位通用计数器,一个是的用到的语法比较全面。是比较好的学习资料...
俩个比较好的计数器的vhdl代码:一个是n位通用计数器,一个是的用到的语法比较全面。是比较好的学习资料-Both a relatively good counter VHDL code: one is the generic n-bit counter, one is the syntax used in the more comprehensive. Is a better learning materials
- 2022-02-21 03:30:56下载
- 积分:1
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Fitz_algorithm
QPSK调制的载波频偏估计,是一个可以调用的函数。接收端进行了一系列的处理。经典的Fitz法(QPSK-carrier frequence offset estimation_ Fitz)
- 2013-03-18 14:37:56下载
- 积分:1