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altera_reed_solomon_design
altera 的reed solomn 设计(reed solomn design from altera)
- 2009-06-14 15:39:32下载
- 积分：1
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2011-diansai-E
2011年 电赛 E题 简易数字信号传输性能分析仪FPGA信号发生部分 包括m序列，伪随机序列，曼彻斯特编码 程序 和单片机部分程序(2011 CEC E title simple digital signal transmission performance analyzer FPGA signal part of the program and single-chip part of the program)
- 2012-02-23 10:11:07下载
- 积分：1
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verilog实现的“六进制约翰逊计数器”。
verilog实现的“六进制约翰逊计数器”。-verilog implementation of the " six hexadecimal Johnson counters."
- 2022-05-10 11:02:11下载
- 积分：1
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《CPLDFPGA verilog DA0832调控
verilog da0832 cpldfpga control-verilog da0832 cpldfpga control
- 2022-12-07 05:55:03下载
- 积分：1
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cf_ad9649_ebz_edk_14_4_2013_03_19.tar
说明： ad9649的fpga驱动程序,FMC接口，基于Xilinx KC705(AD9649 Evaluation Board, FMC Interposer & Xilinx KC705 Reference Design)
- 2020-06-28 14:00:02下载
- 积分：1
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基于vhdl开发的频率发生器
基于vhdl开发的频率发生器-Based on the development of frequency generator vhdl
- 2022-08-19 15:44:18下载
- 积分：1
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counter
本例源代码文件由用户按照书中的操作步骤自己生成，“Example-2-1Project_Navigator_Demo源代码”目录下为源代码的参考文件。“Example-2-1Project_Navigator_Democounter”目录下为完整的工程，包括源代码文件、综合与实现的结果文件、ISE工程文件等，可以使用ISE工程管理器打开工程，供读者参考(In this case the source code files by the user in accordance with the steps the book itself is generated, "Example-2-1 Project_Navigator_Demo source" directory as the source code reference document. "Example-2-1 Project_Navigator_Demo counter" directory for a complete project, including source code files, integrated with the realization of the outcome document, ISE project file, etc. You can use ISE Project Manager, open the project for the reader is referred to)
- 2009-09-19 13:53:10下载
- 积分：1
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LED
是一个LED点阵显示屏的原理图，非常详细，适合开发者学习(LED dot matrix display is a schematic diagram is very detailed, for developers to learn)
- 2011-11-23 00:51:02下载
- 积分：1
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cic_4_dec
实现4倍抽取的CIC抽取滤波器模块的Verilog实现，在对数据进行抽取之前，首先进行滤波(Extracted 4 times realize CIC decimation filter module Verilog realize that in the data collected before the first filter)
- 2008-07-08 16:23:03下载
- 积分：1
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password
verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。(verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.)
- 2011-10-18 21:45:45下载
- 积分：1
