-
all clock
数字钟通过verilog实现,并且支持Modelsim仿真(The digital clock is implemented by Verilog and supports Modelsim simulation)
- 2020-06-18 05:00:01下载
- 积分:1
-
VHDL version of the C8051 core (C8051). Evatronix company s IP core
VHDL版的C8051核(C8051).evatronix公司的IP核-VHDL version of the C8051 core (C8051). Evatronix company s IP core
- 2022-09-22 12:10:03下载
- 积分:1
-
VHDL频率计
采用VHDL编写的频率计,模块划分清晰易懂,基本原理为检测一个闸门脉冲周期内的信号次数,采用四段数码管显示
- 2022-09-17 10:05:04下载
- 积分:1
-
can_init
说明: 通过SPI接口实现FPGA和MCP2515独立CAN芯片通信,功能使用modelsim仿真,实现了配置、接收、发送功能。(The communication between FPGA and MCP2515 independent can chip is realized by SPI interface. The function is simulated by Modelsim, and the function of configuration, receiving and sending is realized.)
- 2020-12-30 09:28:59下载
- 积分:1
-
VHDL参考程序,他们的初学者参考使用
vhdl参考程序,供初学者参考使用-VHDL reference procedures, their use and reference for beginners
- 2022-04-19 08:23:59下载
- 积分:1
-
4锁,移位,可以设置和更改您的密码。
四位密码锁,移位显示,可以设置和更改密码。-4 lock, shift, it can be set up and change your password.
- 2023-05-03 17:05:04下载
- 积分:1
-
T13_USB
本示例为基于FPGA红色飓风一代IDS-EP1C6/12开发板的USB传输,实现了pc端接收来自FPGA开发板的数据,并显示条纹,具体使用说明见解压后的说明文档。(This example is based on red hurricane generation FPGA development board' s USB transfer IDS-EP1C6/12 realized pc client receives the data from the FPGA development board and display stripes, detailed instructions, see the documentation after decompression.)
- 2011-01-05 15:10:38下载
- 积分:1
-
verilog,4、5分频器,5分频器占空比3:2
verilog,4、5分频器,5分频器占空比3:2-Verilog, 4,5 dividers, five dividers ratio of 3:2
- 2022-06-12 21:27:51下载
- 积分:1
-
modulation-and-demodulation
调制与解调系统的FPGA设计实现,包括2-ASK调制和解调,2-FSK调制和解调,2-PSK调制和解调,QPSK调制和解调,PPM调制和解调的verilog源代码。(FPGA design implementation of modulation and demodulation system, including 2-ASK modulation and demodulation, 2-FSK modulation and demodulation, 2-PSK modulation and demodulation, QPSK modulation and demodulation, PPM modulation and demodulation verilog source code .)
- 2021-04-09 09:29:01下载
- 积分:1
-
九层单个电梯的控制系统设计和测试代码rar
说明: 这是一个单个的九层的电梯控制系统的VHDL代码,具有外部上下楼控制按钮和内部上下楼控制按钮。另外还有测试代码。(This is a design of nine floor lift control system with VHDL code and testbench.)
- 2020-06-19 22:03:11下载
- 积分:1