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VHDL语言实现PWM信号，非常方便的使用
VHDL语言实现PWM信号，非常方便的使用-VHDL language realize PWM signal, very convenient to use
- 2022-04-25 12:01:37下载
- 积分：1
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在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。...
在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变ＰＮ码结构可以作为通用数列检测器-QuartusII use in AHDL language, the first PN generator designed to generate a data stream 11 throughout the cycle has an effective data = 2047 re-designing the state machine used to detect the serial data stream in sequence. The use of two counters were counting on the PN code, as well as counting the number of sequences occur. Changes in the structure of PN code series can be used as general-purpose detector
- 2023-03-11 09:20:03下载
- 积分：1
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sine-wave-in-UPS
正弦波UPS中的逆变电路 包括原理分析 框图 及原理图(Sine wave UPS inverter circuit the principle analysis block diagram and schematic)
- 2013-03-20 10:13:13下载
- 积分：1
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adding
加法器，输入两个整数，用电路图形式将其逻辑原理呈现出来，该加法器为8位运算，每一位都对应一张电路图，可展示其完整过程(Adder, input two integer, with circuit diagram form its logical principle appear, this adder is 8 bit arithmetic, each corresponding to a circuit diagram, can show the complete process)
- 2012-11-19 13:54:32下载
- 积分：1
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cordic
基于cordic算法的DDS的Verilog代码。经过仿真验证，绝对可靠。(Based on cordic algorithm DDS Verilog code. Through the simulation, is absolutely reliable.)
- 2013-12-20 17:22:38下载
- 积分：1
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chenxu
电子时钟，可以显示四位，两位显示分钟，两位显示秒，可以用按键控制清零，以及加减数(Electronic clock, you can display four bit, two bit display minutes, the second display seconds, can be used to control the key to clear, and the addition of subtraction)
- 2017-04-22 21:29:14下载
- 积分：1
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Advanced-FPGA-Design
高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)
- 2021-04-01 11:09:08下载
- 积分：1
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FMCOS
复旦cpu COS
- 2015-12-23 15:53:42下载
- 积分：1
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ethernet_mac-master
ethernet mac vhdl verilog basic
- 2019-03-30 15:47:25下载
- 积分：1
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Service-Manual-LG-TV-LCD-DISPLAY-models-2011
Service Manual LG TV LCD DISPLAY models 2011
- 2012-11-22 10:26:51下载
- 积分：1
