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在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。...
在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变ＰＮ码结构可以作为通用数列检测器-QuartusII use in AHDL language, the first PN generator designed to generate a data stream 11 throughout the cycle has an effective data = 2047 re-designing the state machine used to detect the serial data stream in sequence. The use of two counters were counting on the PN code, as well as counting the number of sequences occur. Changes in the structure of PN code series can be used as general-purpose detector
- 2023-03-11 09:20:03下载
- 积分：1
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verilog编写的流水线模块
verilog编写的流水线模块-Verilog modules prepared by the Pipeline
- 2022-03-30 09:04:46下载
- 积分：1
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华为经典FPGA设计全套入门技巧
华为经典设计全套入门技巧，面试经验，设计技巧(Huawei Classic Design Complete Introduction Skills, Interview Experience, Design Skills)
- 2020-07-01 23:00:02下载
- 积分：1
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这是使用VHDL编写的交通灯程序,供大家交流学习
这是使用VHDL编写的交通灯程序,供大家交流学习-This is the use of VHDL prepared by the traffic lights procedures for the exchange of learning
- 2022-04-29 16:41:55下载
- 积分：1
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第七次课--视频图像DCT处理及水印嵌入_2
说明： 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
利用双线性插值方法实现对图像640×480到1024×768的放大操作。
完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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SRAM_16Bit_512K
说明： VHDL语言写的SRAM控制程序，在开发板上验证过。(Written in VHDL SRAM control procedures, the development board verified.)
- 2010-05-04 09:12:20下载
- 积分：1
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AN66806
提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码(Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code)
- 2013-08-13 14:42:55下载
- 积分：1
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Hexadecimal to 7 segments
Hexadecimal to 7 segments
- 2022-03-07 14:40:55下载
- 积分：1
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MIL-STD-1553B代码
FPGA实现1553B编解码器功能 Verilog语言(FPGA implementation of 1553B codec function, Verilog language)
- 2020-12-04 16:29:25下载
- 积分：1
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vhdl的3
vhdl的3-8译码器-instantiate the 3-8 decoder
- 2022-03-25 00:36:10下载
- 积分：1
