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ahb_master_monitor
AHB master monitor for verification
- 2015-04-03 19:38:06下载
- 积分:1
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VHDL-Handbook.pdf
VHDL Handbook by HARDI Electronics AB
- 2015-02-17 17:50:32下载
- 积分:1
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开发系统上采用的时钟信号的频率是20MHz,可分别设计计数器对其计数,包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出,这样就构成了一个电子日历和时钟...
开发系统上采用的时钟信号的频率是20MHz,可分别设计计数器对其计数,包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出,这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值,还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit
- 2022-08-07 06:47:58下载
- 积分:1
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是用VHDL语言写的对A/D转换模块的控制程序,希望对大家有帮助。...
是用VHDL语言写的对A/D转换模块的控制程序,希望对大家有帮助。-VHDL language is used on the A/D conversion module control procedures, in the hope that everyone has to help.
- 2023-05-25 06:40:03下载
- 积分:1
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md5
MD5 算法在Xilinx FPGA上的实现,希望对大家有用。(MD5 algorithm in Xilinx FPGA Implementation, in the hope that useful to everyone.)
- 2021-04-19 15:18:51下载
- 积分:1
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VHDLFIR
1 由matlab计算FIR数字滤波器的滤波系数;
2 用VHDL语言设计逻辑电路,再通过QUARTUS II 软件,将各个模块的电路封装成期间,在顶层设计中通过连线,完成整个系统。
(matlab
VHDL
QUARTUS )
- 2016-05-15 12:49:30下载
- 积分:1
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增强型8051的VHDL源代码,两个周期执行一条指令,仿真工具为Modelsim,开发板为Altera的EP1C20开发板...
增强型8051的VHDL源代码,两个周期执行一条指令,仿真工具为Modelsim,开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board
- 2022-07-06 19:09:46下载
- 积分:1
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Based on quartus a 3
基于quartus的3-8译码器,可作为大型系统的译码器模块-Based on quartus a 3-8 decoder can be used as large-scale system decoder module
- 2022-03-14 15:00:50下载
- 积分:1
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ex11
说明: 该模块实现了FPGA的uart串口收发功能(The module realizes UART serial port transceiver function of FPGA)
- 2020-09-09 11:58:09下载
- 积分:1
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vhdlcoder
VDHL的简单DEMO演示,有利于初学者学习使用(VDHL simple demo DEMO will help beginners learn to use)
- 2008-01-16 15:44:44下载
- 积分:1