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Temperature measurement
Using LabVIEW FPGA, Spartan3E, PMODTMP
Temperature measurement
Using LabVIEW FPGA, Spartan3E, PMODTMP
- 2022-03-05 00:22:10下载
- 积分：1
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dac5686
在FPGA上编写的通过SPI总线配置外部DAC芯片DAC5686的程序，通过板级调试，验证可用。程序通过状态机实现，将需要配置的寄存器值转为SPI总线的数据格式发送出去。 (Configure external DAC chip DAC5686 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you will need to configure the register values 椠渀琀漀 SPI bus data format sent.)
- 2014-09-11 11:05:20下载
- 积分：1
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asynchronous reset state machine
异步复位状态机
-- State Machine with Asynchronous Reset
-- dowload from: www.fpga.com.cn & www.pld.com.cn
-asynchronous reset state machine-- State Machine with Asynchronou "s Reset-- dowload from : www.fpga.com.cn
- 2023-07-14 12:30:03下载
- 积分：1
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步进电机
此代码是用于旋转一个步进电机所需的方向。
- 2022-10-22 10:05:04下载
- 积分：1
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8位相 加乘法器，具有高速，占用资源较少的优点
8位相 加乘法器，具有高速，占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages
- 2023-05-06 21:10:02下载
- 积分：1
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ripple adder
设计的结构是纹波进位加法器架构，但执行的操作是32位加法和32位减法
- 2023-07-02 19:50:04下载
- 积分：1
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dgnszsz
多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)
- 2013-09-20 10:20:31下载
- 积分：1
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QAM_verilog
基于FPGA的16QAM，用verilog编写，其中DDS为自己编写，含设计文件和testbench。已通过moldesim软件仿真。 (FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.)
- 2021-02-22 18:29:41下载
- 积分：1
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二维高斯实现的Vhdl代码
这段代码是用来实现二维高斯滤波器的。
- 2022-01-25 17:27:16下载
- 积分：1
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SimpleVOut-master
SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals
in various formats. The cores connect using AXI-streams. Most configurations
(resolution, framerate, colordepth, etc.) are set at compile-time using
Verilog parameters. See svo_defines.vh for details on those parameters.
- 2020-06-24 21:20:01下载
- 积分：1
