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吠陀乘数
吠陀乘数
- 2022-01-31 06:52:01下载
- 积分：1
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DW8051单片机的设计，用HDL设计，详细的HDL设计
DW8051单片机的设计，用HDL设计，详细的HDL设计-DW8051 microcontroller design, HDL design, detailed design of the HDL
- 2023-03-12 10:35:03下载
- 积分：1
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RS译码的Euclid算法及其FPGA实现，并通过仿真器的出结果，对于设计ＲＳ译码很有帮助...
RS译码的Euclid算法及其FPGA实现，并通过仿真器的出结果，对于设计ＲＳ译码很有帮助-RS decoding Euclid algorithm and its FPGA implementation, and through the simulator results are helpful for the design of RS decoder
- 2022-08-20 11:45:06下载
- 积分：1
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PSK
实现psk调制解调，vhdl代码，仿真文件也有(psk shixian tiaozhiyujietiao)
- 2013-04-10 14:24:53下载
- 积分：1
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VHDL电子抢答器的实现。有多个文件，主控件是用图行实现。其余各功能模块用VHDL实现...
VHDL电子抢答器的实现。有多个文件，主控件是用图行实现。其余各功能模块用VHDL实现-VHDL electronic Responder realized. A number of documents, the main controls are using maps the bank. The remaining modules using VHDL
- 2022-03-14 00:36:42下载
- 积分：1
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bhas
this is a vhdl program...
- 2013-08-17 23:30:56下载
- 积分：1
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UART
本代码用verilog语言配合sopc和nios实现了串口调试的目的。软件编程用C语言描述，只是比较简单的例子，适合初学者做了解用，本人亲自在EP2C8Q上实践。(The code to use verilog language sopc and nios achieved with serial debugging purposes. Software programming using C language description, but relatively simple example for beginners to do with understanding, I personally EP2C8Q on practice.)
- 2013-09-11 10:48:17下载
- 积分：1
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FPGAshixu
FPGA经验总结：时序是设计出来的
我们在做详细设计的时候，对于一些信号的时序肯定会做一些调整的，但是这种时序的调整最多只能波及到本一级模块，而不能影响到整个设计。(FPGA Experience: Timing is designed to do the detailed design of our time, for some signal timing will certainly make some adjustments, but adjust this timing can only spread to up to this level of the module, but not affect the whole design.)
- 2015-03-13 10:27:51下载
- 积分：1
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HalfbandDec
基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。(Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.)
- 2012-10-25 11:18:40下载
- 积分：1
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md5
MD5 算法在Xilinx FPGA上的实现，希望对大家有用。(MD5 algorithm in Xilinx FPGA Implementation, in the hope that useful to everyone.)
- 2021-04-19 15:18:51下载
- 积分：1
