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turbo_encoder
在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。(Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.)
- 2021-04-19 09:38:51下载
- 积分:1
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通过VHDL语言进行数字信号处理的FIR操作,可以很好的实现滤波功能,有很好的作用,...
通过VHDL语言进行数字信号处理的FIR操作,可以很好的实现滤波功能,有很好的作用,-Through VHDL languages digital signal processing FIR operation, can good realization filtering, have good role
- 2022-06-02 18:18:30下载
- 积分:1
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LatticeECP3_SERDES_PCS_使用指南
LatticeECP3 SERDES/PCS 使用指南(LatticeECP3 SERDES/PCS usage guide)
- 2017-06-13 13:57:27下载
- 积分:1
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Uart2Sdram2TFT_median_filter
说明: 使用FPGA实现中值滤波算法,能够使数据直接使用该系统对数据进行中值滤波。(FPGA is used to realize the median filtering algorithm, which can make the data directly use the system for median filtering.)
- 2019-12-30 21:27:58下载
- 积分:1
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该文件用在CPLD上的,和C语言很接近,5位的计数器一个。
该文件用在CPLD上的,和C语言很接近,5位的计数器一个。-the documents on the CPLD, and the C language is close to that of the five counters one.
- 2023-04-25 23:35:03下载
- 积分:1
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volt_mea_disp
本程序是用verilog 编写的模块,用来在lcd1602上显示用tlc549采样的电压值(This program is written in verilog module, used in lcd1602 display with tlc549 sampled voltage value)
- 2013-07-26 00:58:35下载
- 积分:1
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DMA
针对QUARTUS的DMA的VHDL代码实现(DMA Controller Code in VHDL)
- 2009-07-04 23:14:32下载
- 积分:1
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FPGA realization of the LCD interface, VHDL programming, FPGA chips for Altera
FPGA实现的LCD接口,VHDL编程,FPGA芯片为ALtera公司的EP2c35-FPGA realization of the LCD interface, VHDL programming, FPGA chips for Altera
- 2022-09-14 14:30:09下载
- 积分:1
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ethernet_100
Verilog,编写的udp收发程序,开发环境xilinx(Verilog, written UDP transceiver)
- 2020-10-29 21:09:57下载
- 积分:1
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A signal can be stretched any one CLk the VHDL source code examples. See documen...
一个可以把信号拉长任意个CLk的VHDL源码例子。详见说明文档-A signal can be stretched any one CLk the VHDL source code examples. See documentation
- 2022-03-24 02:54:32下载
- 积分:1