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electronic-lock-and-VHDL-design
基于Max+Plus II和VHDL的电子密码锁设计(Based on Max+ Plus II electronic lock and VHDL design)
- 2011-11-17 10:19:40下载
- 积分：1
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newViterbi217
基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误(IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct)
- 2020-06-29 08:40:01下载
- 积分：1
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几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码
几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
- 2023-05-10 01:55:03下载
- 积分：1
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SR_DDS
DDS信号源设计，有正弦波，方波，三角波，AM波，FM波，还有PSK,FSK,16QAM等多种信号产生。(DDS signal source design, there are sine, square wave, triangle wave, AM wave, FM wave, as well as PSK, FSK, 16QAM and other signal generation.)
- 2016-03-20 22:04:51下载
- 积分：1
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硬件仿真
说明： 基于FPGA的QPSK系统仿真及验证，硬件部分。(Simulation and verification of QPSK system based on FPGA)
- 2021-02-06 16:21:17下载
- 积分：1
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spi_dac_ad7394_ad7395.v
Verilog code of SPI configurator for DAC AD7394 and AD7395
- 2014-09-11 21:58:15下载
- 积分：1
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1pps
说明： fpga程序，产生1pps脉冲信号，使用的verilog语言。(FPGA program generates 1 PPS pulse signal, using Verilog language.)
- 2020-06-20 17:00:01下载
- 积分：1
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within waveform generator, Adder, classic dual
内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
- 2023-09-02 09:40:03下载
- 积分：1
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CalcJavaCRC
This programa execute calc of CRC by use a table.
- 2014-08-21 23:04:30下载
- 积分：1
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SV-Combinational-Logic
system Verilog combinational logic
- 2017-01-24 18:50:29下载
- 积分：1
