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16位浮点FFT算法的VHDL实现有测试文件！
16位浮点FFT算法的VHDL实现有测试文件！-16-bit floating-point FFT algorithm VHDL realization of a test file!
- 2022-01-28 18:16:34下载
- 积分：1
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arccos
一个求反余弦的cordic算法，整个工程。包括仿真。可以直接打开。(An inverse cosine of the cordic seeking algorithms, the whole project. Including the simulation. Can be directly opened.)
- 2009-11-04 22:48:00下载
- 积分：1
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S04_基于ZYNQ的HLS 图像算法设计基础
说明： VIVADO HLS IMAGE 使用文档(vivado image processing example text of zynq)
- 2020-06-17 11:40:02下载
- 积分：1
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for Dictyophora board, in the way of achieving LCD clock function.
适合DE2板，能够在板子上的液晶显示器上实现时钟功能。-for Dictyophora board, in the way of achieving LCD clock function.
- 2023-08-10 07:45:03下载
- 积分：1
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spartanII 是xilinx公司提供的一款高性能FGPA芯片,本文详细介绍spartanII的体系结构和编程!...
spartanII 是xilinx公司提供的一款高性能FGPA芯片,本文详细介绍spartanII的体系结构和编程!-spartanII Xilinx is provided by a high-performance chip FGPA, spartanII This paper describes the architecture and programming!
- 2022-03-03 02:06:35下载
- 积分：1
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Routine application of this experiment in the Actel Flash architecture ProASIC3/...
此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA，适合于FPGA及Verilog HDL的初学者，配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development kit EasyFPGA030.
- 2022-05-14 23:14:31下载
- 积分：1
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FPGA-design-and-application
已经正式出版，西安电子科技大学出版社，FPGA设计及应用，作者褚振勇(Has been officially published, Xi' an University of Electronic Science and Technology Publishing House, FPGA design and application, the author Zhezhengyong)
- 2009-06-03 15:57:31下载
- 积分：1
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tongbu
使用VERILOG开发时钟同步算法，能够从数据信号中提取时钟信息，(Clock synchronization algorithm using VERILOG developed to extract the clock from the data signal information,)
- 2020-11-11 12:39:44下载
- 积分：1
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VHDL-the-count
利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发
时钟，计数器进行加计数，并利用数码管进行显示，当计数到9999 时，从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger
The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count
)
- 2012-01-13 14:01:38下载
- 积分：1
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freq
vhdl八位十进制数字频率计的设计，顶层和数码管扫描模块(vhdl eight decimal digital frequency meter design, top-level and digital tube scanning module)
- 2012-10-09 15:09:22下载
- 积分：1
