登录
首页 » VHDL » 用数码管显示时间的数字电子钟verilog编写

用数码管显示时间的数字电子钟verilog编写

于 2022-06-22 发布 文件大小:3.44 kB
0 6
下载积分: 2 下载次数: 2

代码说明:

用VERILOG编写的数字电子钟,用数码管进行显示时间-VERILOG prepared with digital electronic clock with a nixie tube display time

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • cic
    cic设计 verilog verilog(cic verilog design verilog)
    2012-10-23 20:13:52下载
    积分:1
  • pcf8563
    pcf8563,在quartusII下VERILOG编写的数字时钟程序,8位数码管显示(pcf8563, written in quartusII VERILOG digital clock program, eight digital display)
    2013-12-24 21:46:21下载
    积分:1
  • IIR-digital-filter-
    采用双线性变换法设计IIR数字滤波器设计的c代码,包括低通、高通和带通(Document recording the design of IIR digital filter c code)
    2011-09-05 17:47:58下载
    积分:1
  • Modulation
    产生长度为100的随机二进制序列 发送载波频率为10倍比特率,画出过采样率为100倍符号率的BPSK调制波形(前10个比特) ,及其功率谱 相干解调时假设收发频率相位相同,画出x(t) 的波形,假设低通滤波器的冲激响应为连续10个1(其余为0),或连续12个1 (其余为0) ,分别画出两种滤波器下的y(t),及判决输出(前10个比特) 接收载波频率为10.05倍比特率,初相位相同,画出x(t) 的波形,假设低通滤波器的冲激响应为连续10个1,画出两种滤波器下的y(t),及判决输出(前20个比特) 采用DPSK及延时差分相干解调,载波频率为10倍比特率,画出a, b, c, d点的波形(前10个比特) DPSK及延时差分相干解调,载波频率为10.25倍比特率时,画出a, b, c, d点的波形(前10个比特) DPSK及延时差分相干解调,载波频率为10.5倍比特率时,画出a, b, c, d点的波形(前10个比特) (Produce random binary sequence of length 100 The transmission carrier frequency is 10 times the bit rate, draw a sampling rate of 100 times the symbol rate of the BPSK modulation waveform (first 10 bits), its power spectrum Coherent demodulation of assuming the same as the phase of the transmitting and receiving frequencies, and draw the waveform x (t), assuming that the impulse response of the low pass filter 10 consecutive 1 (the remainder is 0), or 12 consecutive 1 (the remainder is 0), y (t) is drawn under the two filters respectively, and the decision output (10 bits) The received carrier frequency is 10.05 times the bit rate, the same initial phase, draw the waveform x (t), assuming that the impulse response of the low pass filter of 10 consecutive 1, shown under two filter y (t), and decision output (20 bits) DPSK and delay differential coherent demodulation, the carrier frequency is 10 times the bit rate, draw a, b, c, d point of the waveform (first 10 bits) DPSK and delay)
    2020-12-14 08:19:14下载
    积分:1
  • 按键控制led
    按键控制led灯亮灭顺序,从左到右跑或者从右往左跑(Press button to control the LED lights on and off)
    2017-06-30 10:37:30下载
    积分:1
  • 高密度脂蛋白示例源代码5 / 1
    HDL example source code 1/5 dff_as
    2022-03-13 02:50:40下载
    积分:1
  • dds
    说明:  实现数字频率合成实验,加载数据ram,形成波形(The experiment of digital frequency synthesis is realized, and the data RAM is loaded to form the waveform)
    2020-11-10 18:12:36下载
    积分:1
  • I2C_CSDN
    说明:  verilog 编写的I2C程序,控制D/A的(I2C program written by Verilog to control D/A)
    2020-06-18 21:20:02下载
    积分:1
  • AM-modulated-learning-ladder
    AM modulated learning ladder
    2015-07-15 09:42:45下载
    积分:1
  • ex4
    statemachine project for my school
    2011-12-02 21:07:27下载
    积分:1
  • 548251资源总数
  • 51198会员总数
  • 190今日下载