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EDA
计数器的程序，eda编程用的，vhdl语言编程，大家下载看看吧(Program counter, eda programming used, vhdl programming
)
- 2010-12-22 20:47:02下载
- 积分：1
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divisor
Time divisor vhdl code
- 2009-06-02 21:31:05下载
- 积分：1
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DE2_PS2_Debug
这是altera公司的DE2-35开发板下的一个PS2键盘的源程序代码工程，包括PS2驱动等模块有需要的人，可以下载(Altera DE2-35 development board of the company, the source code of a PS2 keyboard works, including the the PS2 driver modules need, you can download)
- 2012-10-19 20:55:20下载
- 积分：1
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它的译码器的VHDL程序
it s vhdl program for decoder
- 2022-11-23 15:15:04下载
- 积分：1
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Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
- 2022-06-13 02:00:08下载
- 积分：1
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Cadence-Allegro-PCB-SI
利用Cadence Allegro PCB SI进行SI仿真分析(Performed using the Cadence Allegro PCB SI SI simulation analysis)
- 2013-08-06 22:17:46下载
- 积分：1
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如果不考虑占空比，直接利用计数器来进行分频，则占空比会发生变化。下面程序实现1：1的三分频。...
如果不考虑占空比，直接利用计数器来进行分频，则占空比会发生变化。下面程序实现1：1的三分频。-if not duty cycle directly counter to the use of sub-frequency, duty cycle will change. Below a program : a third of the frequency.
- 2022-01-21 05:34:37下载
- 积分：1
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VHDL经典教程,下了不会后悔
VHDL经典教程,下了不会后悔-VHDL Tutorial classic, the next will not regret it
- 2022-01-25 20:37:44下载
- 积分：1
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FRFT_Ozaktas
这是分数阶傅里叶变换FRFT的土耳其算法的FPGA实现的程序，FPGA是Xilinx的virtecx-5，这是我在做毕业设计的时候自己编写的，希望能对你有帮助！(This is the fractional Fourier transform algorithm FRFT Turkish FPGA implementation of the program, FPGA is the Xilinx virtecx-5, which is what I was doing graduate design time I have written, I hope you can help!)
- 2021-03-12 10:49:25下载
- 积分：1
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Describes how to use VHDL language processor spi interface
介绍了如何用vhdl语言实现处理器的spi接口-Describes how to use VHDL language processor spi interface
- 2022-07-22 21:57:12下载
- 积分：1
