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FIFO
Simulation and Synthesis Techniques for Asynchronous
FIFO Design
- 2013-08-27 16:07:08下载
- 积分：1
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双向移位寄存器的VHDL源程序,自己做实验编写的可以用 谢谢大家...
双向移位寄存器的VHDL源程序,自己做实验编写的可以用 谢谢大家-Bi-directional shift register of the VHDL source code, prepared by their own experiments can be used Thank you
- 2022-02-11 10:52:42下载
- 积分：1
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本文是自已写的电子密码锁的详细开发过程，用的是Modelsim进行仿真实现，打开文档lzp...
本文是自已写的电子密码锁的详细开发过程，用的是Modelsim进行仿真实现，打开文档lzp-This article is written in their own electronic locks detailed development process, using a ModelSim simulation achieved, open the document lzp
- 2022-01-25 15:10:58下载
- 积分：1
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fpga
简易数字存储示波器verilog源代码 经过EP2C8Q208C8验证(Simple digital storage oscilloscope verilog source code has been verified EP2C8Q208C8)
- 2013-07-16 13:04:03下载
- 积分：1
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fft_32k_readme_v1_0_0
Fast Fourier Transform (FFT) 32K Point Design contains
information about the design example
- 2018-10-11 15:11:54下载
- 积分：1
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这是使用VHDL编写的交通灯程序,供大家交流学习
这是使用VHDL编写的交通灯程序,供大家交流学习-This is the use of VHDL prepared by the traffic lights procedures for the exchange of learning
- 2022-04-29 16:41:55下载
- 积分：1
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relay_test
Simple relay trigger
- 2015-01-28 12:16:35下载
- 积分：1
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ASIC_LIB
ASIC设计中常用的运算模块，如加减，常系数乘法，截断，饱和等。(some modules used in ASIC design.)
- 2010-03-10 15:52:28下载
- 积分：1
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05_fifo_test
说明： FIFO: First in, First out 代表先进的数据先出，后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO，根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)
- 2021-04-08 22:19:20下载
- 积分：1
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rom_fft
采用xilinx的ROMIP核产生类似正弦信号，经过FFt后可以观察结果(Using the xilinx ROMIP nuclear generating similar sinusoidal signal can be observed through the results after FFt)
- 2013-09-14 20:59:03下载
- 积分：1
