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基于Actel A3P030 FPGA液晶显示器使用jdl12864串行接口,时钟可调
基于Actel A3P030 FPGA,液晶采用JDL12864串行接口,时钟48MHz-Based on Actel A3P030 FPGA, LCD using JDL12864 serial interface, clock 48MHz
- 2022-07-05 03:00:11下载
- 积分:1
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计数器的VHDL语言
这个程序VHDL计数器计数二进制数并显示脉冲易于程序计数器的VHDL,我们需要了解逻辑电路的VHDL语言的程序员
- 2022-12-04 13:20:03下载
- 积分:1
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CPU-Verilog
简单流水线CPU,使用 verilog实现,实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)
- 2020-06-23 19:40:01下载
- 积分:1
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electronic-lock-and-VHDL-design
基于Max+Plus II和VHDL的电子密码锁设计(Based on Max+ Plus II electronic lock and VHDL design)
- 2011-11-17 10:19:40下载
- 积分:1
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ppmencoder
一个八位的并行输入,串行输出的编码器;带有开头结尾帧。(It is an encode with eight palallel input and a serial output.)
- 2020-11-23 01:19:34下载
- 积分:1
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利用Verilog HDL对AD7705进行控制ADC采样,实验室师兄的
利用Verilog HDL对AD7705进行控制ADC采样,实验室师兄的-Using Verilog HDL to the AD7705 control ADC sampling, laboratory师兄the
- 2023-01-10 03:55:04下载
- 积分:1
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GPS
通过UART在FPGA数码管上显示经纬度坐标的代码(By UART displayed on FPGA digital latitude and longitude coordinates of the code)
- 2015-06-22 17:14:37下载
- 积分:1
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reversible-squarer
it is hybrid squarer circuit which will be designed using reversible gates which having les hardware complexity with compared to the conventional gates
- 2015-04-21 15:05:54下载
- 积分:1
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8051IP nuclear source code (VHDL). RAR
8051IP 核源代码(VHDL).RAR-8051IP nuclear source code (VHDL). RAR
- 2022-11-14 08:05:04下载
- 积分:1
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利用两个半加器来组成的全加器,是简单的vhdl语言入门
利用两个半加器来组成的全加器,是简单的vhdl语言入门-The use of two and a half adder to form the full adder is a simple entry-vhdl language
- 2023-08-01 03:35:04下载
- 积分:1