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edge_detect_p
用于检测信号上升沿，输出与时钟相关的正脉冲(Detect the rising edge of the signal)
- 2012-03-27 14:49:21下载
- 积分：1
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Verilog_HDL
华为文档《硬件描述语言Verilog基础》-目录
原来搞VHDL，刚刚开始学Verilog。觉得这个入门的提纲不错，共享一下。
(Huawei Documents " basic Verilog Hardware Description Language" - the original directory engage in VHDL, just beginning to learn Verilog. Feel that the entry of the outline of a good, share some.)
- 2009-02-21 18:02:37下载
- 积分：1
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The use of Altera' s FPGA
使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个RAM存储器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a RAM memory.
- 2023-04-02 08:45:02下载
- 积分：1
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Endat_2
Endat slave interface
- 2021-04-21 19:38:49下载
- 积分：1
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FPGAVHDL
vhdl例程代码大全，包含流水灯，数码管，AD,DA转换等(Guinness vhdl code routines, including water lights, digital, AD, DA conversion)
- 2020-12-17 12:19:13下载
- 积分：1
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MATLABABCv2
The aim of the ECG simulator is to produce the typical ECG waveforms of different leads and as many arrhythmias as possible. My ECG simulator is a matlab based simulator and is able to produce normal lead II ECG waveform.
- 2017-08-21 21:31:42下载
- 积分：1
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OFDM_802_11
ofdm的发射链路和接收链路的Verilog源代码，包括长短训练序列的生成，导频插入，加cp，ifft。(Source code of transmission link and reception link of OFDM)
- 2020-12-22 21:19:06下载
- 积分：1
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This is a use of the VHDL language Parallel to Serial procedures, In altera deve...
这是一个用VHDL语言编写的并口转串口程序，在altera开发系统下验证通过，运用于开发板与计算机之间的通信，源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communications, can provide a reference source
- 2022-03-23 13:41:19下载
- 积分：1
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VHDL实现SPI功能源代码
VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave shift their shift registers 8 bits and thus exchange their 8
-- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
- 2022-01-26 00:50:40下载
- 积分：1
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verilog写的数字频率计的控制模块,对程序进行控制
verilog写的数字频率计的控制模块,对程序进行控制-written in Verilog digital frequency meter control module, the program control
- 2022-02-04 00:52:27下载
- 积分：1
