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DDSVHDLCODE
本人收集的多个VHDL语言编写的正弦波发生器以及SPWM程序。(I collected multiple VHDL language of sine wave generator SPWM program.)
- 2021-04-06 22:39:02下载
- 积分：1
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proficient VerilogHDL : IC design example explanation of the core technology
精通VerilogHDL：IC设计核心技术实例详解-proficient VerilogHDL : IC design example explanation of the core technology
- 2022-05-07 13:04:08下载
- 积分：1
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基于FPGA的CPU核及其虚拟平台的设计与实现
基于FPGA的CPU核及其虚拟平台的设计与实现-FPGA-based CPU core and its virtual platform design and implementation of
- 2022-08-08 02:35:45下载
- 积分：1
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sdram-control-verilog
SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。(This readme file for the SDR SDRAM Controller includes information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.)
- 2009-12-11 15:01:46下载
- 积分：1
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ozgul2013
说明： Digital pre-distortion (DPD) is an advanced digital
signal-processing technique that mitigates the effects of power
amplifier (PA) nonlinearity in wireless transmitters. DPD plays
a key role in providing efficient radio digital front-end (DFE)
solutions for 3G/4G basestations and beyond. Modern FPGAs
are a promising target platform for the implementation of flexible
wireless DFE solutions, including DPD.
- 2019-01-05 18:20:30下载
- 积分：1
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本设计是针对LEON3 Altera Nios II startix2
This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the
- 2022-05-18 19:00:04下载
- 积分：1
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RS-422standardmodulev2
rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)
- 2013-12-23 14:14:18下载
- 积分：1
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等精度测试频率计，包括程序源代码以及相关注释
等精度测试频率计，包括程序源代码以及相关注释-Precision test frequency meter, etc., including source code and related comments ......
- 2022-04-08 21:00:44下载
- 积分：1
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docs
papers based on distributed arithmetic.
- 2014-02-06 16:17:09下载
- 积分：1
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Modelsim_SDRAM
本实例用于SDRAM完成读写功能:
先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。(The examples for SDRAM read and write functions.)
- 2013-02-06 10:38:14下载
- 积分：1
