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MRAM2012
STT-MRAM磁性存储器全部verilog代码和仿真验证代码，包括行为模块，读写模块和控制模块，已经经过验证完全正确(STT-MRAM magnetic memory all the code and simulation code, including behavior module, reader module and the control module, has been proven entirely correct)
- 2020-06-29 14:20:02下载
- 积分：1
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7_to_1-LVDS-dispaly-from-FLASH
该代码是基于verilog 实现的代码，可以用于对接受1080P的LVDS视频数据并处理后显示到各种规格的LCD屏幕上，且支持从FLASH中读取BMP的图片数据并实时显示到LCS屏幕(The code is based on the code verilog achieve, it can be used for receiving LVDS 1080P video and data processing displayed on a variety of LCD screen, and support for reading data the FLASH BMP images and real-time display to the LCS screen)
- 2016-02-18 14:06:22下载
- 积分：1
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esvl
MATLAB Filter Design HDL Coder
Simunlink HDL Coder
Xilinx ISE Webpack
- 2011-06-15 19:56:11下载
- 积分：1
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这个程序执行的复用与解复用
this program performs multiplexing and demultiplexing
- 2022-10-04 09:30:03下载
- 积分：1
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一个完整的viterbi译码程序和测试的程序
一个完整的viterbi译码程序和测试的程序-A complete viterbi decoding procedures and test procedures
- 2023-01-14 14:40:03下载
- 积分：1
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dds
DDS实验 matlab 与quartus 的完美结合(DDS experimental combination of matlab and quartus)
- 2010-05-08 08:51:48下载
- 积分：1
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跑马灯程序FPGA
FPGA跑马灯程序,基于CPLD1270开发板的运用程序-Marquee program FPGA-based development board CPLD1270 the use of procedures
- 2022-02-04 16:36:32下载
- 积分：1
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rfid new code
说明： In the data management system a significant role of the Data link layer is to convert the unreliable physical link between reader and tag into a reliable link. Therefore, the RFID system employs the Cyclic Redundancy Check (CRC) as an error detection scheme. In addition for reader to communicate with the multiple tags, an anti-collision technique is required. The technique is to coordinate the communication between the reader and the tags. The common deterministic anti-collision techniques are based on the Tree algorithm such as the Binary Tree and the Query Tree algorithms.
- 2019-04-30 16:54:27下载
- 积分：1
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the_last
VHDL语言实现两个人掷骰子游戏，最多6次，大者胜则结束游戏并在点阵上显示，一直平手则一直进行直到达到6次。(Achieving the dice game between two people by using VHDL language.The maximum number of times is 6.The game will over when there is a biger one in one time,otherwise,the game will continue until the time of the game is up to 6.)
- 2021-01-21 12:18:42下载
- 积分：1
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0到255任意整数半整数分频Verilog HDL.rar
0到255任意整数半整数分频Verilog HDL.rar-0-255 arbitrary integer half-integer frequency division Verilog HDL.rar
- 2022-02-06 06:46:57下载
- 积分：1
