登录
首页 » VHDL » 数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;...

数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;...

于 2023-07-21 发布 文件大小:7.03 kB
0 95
下载积分: 2 下载次数: 1

代码说明:

数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • G.hnMAC层功能代码MPDU ASSEMBLER
    G.hnMAC层功能代码,实现了MPDU的资源调度(G.gn MAC codeG.gn MAC codeG.gn MAC code)
    2011-05-18 11:23:08下载
    积分:1
  • PERI4-DM9000A
    基于FPGA的DM9000A芯片的网络数据采集系统,基于NIOS架构,c语言编程,资料齐全,包含不止5个源程序,绝对受用!(FPGA-based the DM9000A chip network data acquisition system based on NIOS architecture, c programming language, the information is complete, contains more than 5 source code is absolutely good enough!)
    2020-09-16 16:57:55下载
    积分:1
  • 8位CPU的VHDL设计代码没有测试
    8 bit cpu vhdl design code not tested
    2022-03-21 20:07:37下载
    积分:1
  • 8位深,9位宽FIFO VHDL源码设计,如需改进可在此基础上扩展
    8位深,9位宽FIFO VHDL源码设计,如需改进可在此基础上扩展-8 deep, 9-bit wide FIFO VHDL source design, for improving on this basis can be extended
    2023-06-13 12:25:03下载
    积分:1
  • 该项目是用于执行4位arethmatic操作和逻辑操作…
    The project is used to perform the operation of 4 bit arethmatic and logical operation. the projcet is implemented in spartan 3E
    2022-03-21 15:49:24下载
    积分:1
  • ddr3_sun
    使用DDR3IP核进行仿真,写入读取数据(Using DDR3IP core to simulate, write and read data)
    2021-01-07 00:48:53下载
    积分:1
  • 互联网测试和检测垃圾邮件
    A 凸轮是一个转动或滑动的片断,在机械联动使用特别是在将旋转运动转变为直线运动或反之亦然。 请点击左侧文件开始预览 !预览只提供20%的代码片段,完整代码需下载后查看 加载中 侵权举报
    2022-02-15 23:05:25下载
    积分:1
  • FPGA2-DSP2-EDMA
    例程是基于quartus的,FPGA通过EMIF给DSP发送数据,里面包含了一个简单的状态机和一个基于IP核的fifo,适合初学者(Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners)
    2020-12-04 16:09:24下载
    积分:1
  • vhdl的仿真 quartus 2的flv视频
    vhdl的仿真 quartus 2的flv视频 -VHDL simulation of the flv video quartus 2
    2022-04-12 23:18:28下载
    积分:1
  • 93 std
    -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn
    2022-02-25 16:35:00下载
    积分:1
  • 696518资源总数
  • 106161会员总数
  • 5今日下载