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基于Verilog的FFT核
- 2022-10-27 16:20:03下载
- 积分:1
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基于FPGA的快速傅立叶变换实现,适合fpga工程技术人员参考设计...
基于FPGA的快速傅立叶变换实现,适合fpga工程技术人员参考设计-FPGA-based Fast Fourier Transform for fpga reference design engineers
- 2022-12-10 15:50:11下载
- 积分:1
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I2C-AT24C02
I2C总线芯片AT24C02程序设计 C++编程(I2C bus AT24C02 chip program design)
- 2013-05-27 15:01:08下载
- 积分:1
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8051core
8051core-Verilog FPGA的51单片机内核源代码!
-8051core-Verilog FPGA 51 Singlechip kernel source code!
- 2023-02-06 02:20:03下载
- 积分:1
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lab4
lab report for lab 4
- 2019-04-17 21:17:08下载
- 积分:1
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组合电路的设计8位加法器设计(ADD8.vhd)
组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)
- 2022-10-25 12:35:04下载
- 积分:1
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vga
利用FPGA控制VGA显示器显示字符汉字的程序,里面有注释。(VGA display with FPGA control procedures Kanji characters, there are comments.)
- 2013-11-25 11:59:13下载
- 积分:1
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basys3_timing
基于Basys3的数字钟实例,主要用于Basys3、vivado开发环境入门。源码使用VerilogHDL(Based on digital clock instance Basys3, mainly for Basys3, vivado development environment started. Use Code VerilogHDL)
- 2016-03-06 11:08:18下载
- 积分:1
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AXI4_Sim
说明: 实现AXI,AXI-Lite乒乓地址的传输,AXI,AXI-Lite已经封装成内核,可直接修改后使用(Realize the transmission of table tennis address of Axi and Axi Lite. Axi and Axi Lite have been encapsulated into a kernel, which can be directly modified and used)
- 2020-05-31 15:20:16下载
- 积分:1
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VerilogHDL,对初学者很有帮助的,可以一下的!
VerilogHDL,对初学者很有帮助的,可以一下的!-VerilogHDL, very helpful for beginners, you can look in!
- 2023-02-06 11:05:03下载
- 积分:1