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vga
VGA interface using Spartan3E board from DIGILENT.Labview .vi
- 2009-09-23 05:02:44下载
- 积分:1
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dw_ahb_dmac_db
It is Synopsys dmac controller databook
- 2020-10-10 10:27:34下载
- 积分:1
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ces_uvm-1.2_2016.06.tar
说明: uvm lab代码以及uvm1.2源码,带有使用说明文档,可以照着文档一步一步深入了解uvm代码。(The code of UVM lab and the source code of uvm1.2 are provided with instruction documents. You can follow the documents step by step to understand the UVM code.)
- 2020-10-01 09:47:42下载
- 积分:1
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Sigma-Delta ADC的例子
Verilog代码为Sigma-Delta ADC的实现。Verilog是包含testbench。NDIFF V。V的冬天。readmem V。V梳状滤波器。combfilter_tb V。combfilter_wrap.vhd
- 2022-03-22 13:11:17下载
- 积分:1
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4位二进制同步计数器
用Verilog语言实现4位二进制同步计数器的功能(Write a program in Verilog language to implement the fouction of Four binary synchronous counters.)
- 2020-11-20 15:19:37下载
- 积分:1
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Verilog實現32筆資料奇偶归并排序
资源描述透過Verilog來實現奇偶归并排序壓縮檔中包括4 8 16 32筆資料的排序、、、oe_sort_32為32筆資料排序網絡oem_32為32筆資料排序模組
- 2023-01-25 06:20:04下载
- 积分:1
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chuankou
说明: 本实验为UART回环实例,实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx,以及时钟产生模块clk_div。uart_rx将收到的包解析出8位的数据,再传送给 uart_tx发出,形成回环。参考时钟频率为100MHz,波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分:1
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cpu mips
实现多周期mips
设计一个32位MIPS多周期微处理器 具有多种 算数指令:
(Design a 32-bit MIPS microprocessor multi-cycle arithmetic instructions
- 2023-03-29 18:05:04下载
- 积分:1
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实战训练21 SDRAM硬件控制
说明: SDRAM硬件控制,fpga的verilog语言,适合学习(SDRAM hardware control, Verilog language of FPGA, suitable for learning)
- 2020-04-29 11:45:16下载
- 积分:1
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EP2C5
基于FPGA/EP2c5的开发板详细例程,内容丰富,简单易懂(Development board based on more routine FPGA/EP2c5, content rich, easy to understand)
- 2020-12-06 22:59:23下载
- 积分:1