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Regs
一个小寄存器堆,使用参数化编程,附有仿真代码,可直接在vivado(2018.2版本及以后)上运行(A small register heap, using parametric programming)
- 2019-04-03 14:19:55下载
- 积分:1
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Regs
说明: 一个小寄存器堆,使用参数化编程,附有仿真代码,可直接在vivado(2018.2版本及以后)上运行(A small register heap, using parametric programming)
- 2019-04-03 14:19:55下载
- 积分:1
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fffffff
如上图所示, Rst是低电平有效的系统复位信号,Clk是时钟信号。AB[5:0]是地址信号,DB[7:0]是数据信号,wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后,可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后,给出一个Clk周期宽度的脉冲信号start,则系统从存储器0地址处开始读出数据,读出的8位数据从低位开始以3位为一组,每个时钟周期输出一组,即第一个时钟周期输出[2:0]位,第二个时钟周期输出[5:3]位,第三个周期输出1地址的[0]位和0地址的[7:6]位,直至将存储器中64x8数据全部输出。若最后一组不足三位,则高位补0。
(As shown above, Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)
- 2020-11-04 20:39:51下载
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JTAG
边界扫描技术相关资料,含各个模块的介绍。很有参考价值。(JTAG TAG CONTROLLER)
- 2016-02-24 19:10:03下载
- 积分:1
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reed_solom
REEDSOLOMON source code
- 2010-04-30 17:44:52下载
- 积分:1
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StepperMotorDrivepinassign
stepper motor vhdl pin assignments and code
- 2011-08-12 23:15:46下载
- 积分:1
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crc16CCITT
自己用verilog编写的crc16-ccitt码的产生,是并行的。(Crc16-ccitt code written in verilog generate parallel.)
- 2012-12-13 09:46:58下载
- 积分:1
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eth_frame_gen
帧激励产生器,用于VMM仿真中生成所需要帧以供测试所用(the use for test)
- 2012-02-02 22:19:25下载
- 积分:1
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cnt24_t
这是二十四进制计数器的源程序,有需要的同学可以参照一下!(This is 24 hexadecimal counter source, needy students can refer to you!)
- 2008-12-22 09:29:29下载
- 积分:1
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AHB DMA verilog
兼容AMBA 2.0 的DMA源码,具有两个MASTER, 一个SLAVE,通道可配。超级经典的电路结构,可以学习或直接使用,经过验证的。
- 2022-03-16 20:13:09下载
- 积分:1