登录
首页 » VHDL » Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S...

Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S...

于 2022-04-11 发布 文件大小:637.13 kB
0 143
下载积分: 2 下载次数: 1

代码说明:

采用Verilog HDL设计,在Altera EP1S10S780C6开发板上实现 选取6MHz为基准频率,演奏的是梁祝乐曲 - Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S780C6 selects 6MHz is the datum frequency, the performance is Liang wishes the music

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;...
    数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;
    2023-07-21 04:20:04下载
    积分:1
  • SystemVerilog验证++测试平台编写指南
    说明:  基于sv的uvm平台搭建实战,对于验证方法学来说,分层的测试平台是一个关键的概念。虽然分层似乎会使测试平台变得更复杂,但它能够把代码分而治之,有助于减轻工作负担,而且重复利用效率提升。验证平台可以类似分为五个层次:信号层、命令层、功能层、场景层和测试层。(Construction of UVM platform based on SV)
    2020-07-19 16:18:46下载
    积分:1
  • ahb 总线协议
    本文以 VHDL 语言编码得到了 AMBA 与 AHB 总线仲裁。这里在本文中,我们设计了 AMBA 总线协议,将用于多奴隶通信环境,多主
    2022-01-25 21:18:17下载
    积分:1
  • 基于VHDL的I2C程序0005,很不错的论文及程序,,大家快下啊
    基于VHDL的I2C程序0005,很不错的论文及程序,,大家快下啊-based on the I2C procedures VHDL 0005, a very good paper and procedures, we quickly under ah
    2022-03-18 17:11:42下载
    积分:1
  • FPGA讲义适合中等以上读者,主要是FPGA的一些高级应用
    FPGA讲义适合中等以上读者,主要是FPGA的一些高级应用-FPGA notes for readers more than moderate, mainly a number of advanced applications FPGA
    2022-06-16 08:29:17下载
    积分:1
  • CME3000FPGADevelopment-
    针对京微雅阁的CME300 FPGA教程,里面有几个例程,并附有源代码,初学者可尽快入门。(For Beijing micro Accord CME300 FPGA tutorial, there are a few routines, with source code, beginners can start as soon as possible.)
    2013-08-19 18:01:21下载
    积分:1
  • LVDS_RX
    说明:  lvds_rx IP核硬件设计代码,使用时注意LVSD_RX模块的延时参数的设置,3.5倍时钟相位的设置(Lvds IP core hardware design code, when using the attention LVSD module delay parameter settings, 3.5 times the clock phase settings)
    2021-04-26 11:38:45下载
    积分:1
  • fir
    该程序实现了一个FIR滤波加速器,该程序在FPGA板上开发,通过使用VHDL语言来定义RS232端口的使用(design a FIR Filter Accelerator based on FPGA board and RS232 interface using VHDL language. )
    2013-06-07 06:27:32下载
    积分:1
  • fpga clock design, the information is better, for your reference, non
    fpga clock 设计,资料较好,供大家参考,非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh
    2022-10-20 15:50:02下载
    积分:1
  • 32_lvds_test
    Xilinx 公司Spartan-6系列FPGA实现LVDS,带Modelsim仿真文件,已综合。(Xilinx Spartan-6 Series FPGA implements LVDS with Modelsim simulation file, which has been synthesized.)
    2020-11-30 20:59:27下载
    积分:1
  • 696516资源总数
  • 106783会员总数
  • 25今日下载