Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S...
于 2022-04-11 发布
文件大小:637.13 kB
0 111
下载积分: 2
下载次数: 1
代码说明：
采用Verilog HDL设计，在Altera EP1S10S780C6开发板上实现 选取6MHz为基准频率，演奏的是梁祝乐曲 - Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S780C6 selects 6MHz is the datum frequency, the performance is Liang wishes the music
下载说明：请别用迅雷下载，失败请重下，重下不扣分！
发表评论
