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Viterbi译码器IP核,可以直接编译使用
viterbi译码器的IP核,可以直接编译使用-viterbi decoder IP core, the compiler can directly use
- 2023-01-24 09:35:04下载
- 积分:1
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vhdl coding for Carry Select Adder
这是一个vhdl代码的进位选择加法器及其工作100%。
- 2023-08-26 17:05:04下载
- 积分:1
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jiecheng
利用Verilog语言中的函数调用实现阶乘运算的功能(Function calls use Verilog language implementation of the factorial function computing)
- 2016-05-16 21:01:23下载
- 积分:1
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sinwave
使用verilog hdl语言编程正弦波信号,能仿真出结果(Can use verilog HDL language programming sine wave signal, the simulation results
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- 2013-09-18 15:27:27下载
- 积分:1
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uart-for-fpga
说明: Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA.
Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit!
The UART controller was simulated and tested in hardware.
- 2020-06-24 22:00:02下载
- 积分:1
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这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章,实用性很强的,在这里也感谢这篇文章的作着...
这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章,实用性很强的,在这里也感谢这篇文章的作着-This is a description language with verilog viterbi decoding and rake receiver of the article, very practical, here are grateful for this article was
- 2022-05-13 15:53:30下载
- 积分:1
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fft64
使用两个8点FFT完成64-point FFT(64-point FFT)
- 2013-01-15 04:57:52下载
- 积分:1
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pps_ketiao_rb2
FPGA程序,使用Verilog语言生成1个脉冲可调的PPS脉冲信号。(FPGA program generates 1 PPS pulse signal, using Verilog language.)
- 2020-06-20 17:00:02下载
- 积分:1
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xilinx原语的使用方法
说明: Xilinx原语的使用介绍,特别全面,希望对大家有所帮助,(Introduction to the use of Xilinx primitives, particularly comprehensive,I hope it will be helpful to you all.)
- 2019-04-16 22:50:07下载
- 积分:1
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reader
实现verilog读写txt文件,从sut.txt从读取数据,进行操作后,写入out.txt(Realize verilog read and write txt file)
- 2020-11-15 21:29:41下载
- 积分:1