带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client

TCM解码，VHDL代码，是我在工作中做的工程代码，时序稳定，里面有syn以及软判决的算法，经典-TCM decoder, VHDL code, yes, I do work in the project code, timing stability, There are syn and soft-decision algorithm, classic!

cordic implementation in vhdl&c

48阶FIR设计，采用VHDL语言描述，门级映射……(48-oders FIR design with VHDL language and gate level)

说明：  Verilog开发的，MII接口的百兆以太网UDP代码(100 megabit Ethernet UDP code of MII interface)

数字电子琴控制器的ＶＥＲＩＬＯＧ代码，含中文注释．-The number of organ controller Verilog code, with English Notes.

这个是用VHDL实现FPGA对FLASH的读写。(This is achieved using VHDL FLASH FPGA to read and write.)

合众大公司XILINX_V4实验箱原理图-United XILINX_V4 large companies schematic experimental box

ARM7 VERILOG源码，非常精简，3级流水线(ARM7 VERILOG source code, very streamlined, 3-stage pipeline)

说明：  可以获取各种字符，并在数码管显示出来，非常的靠谱且稳定(Various characters can be acquired and displayed on the digital tube.)