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chengxu
设计制作一个可容纳4组参赛者的数字智力抢答器，每组设置一个抢答按键；
电路具有一第一抢答信号的鉴别和锁存的功能。在主持人将系统复位并发出抢答指令后，若参加者按抢答键，则该组指示灯亮并用组别显示抢答者的组别。此时，电路具有自锁功能，使别组的抢答开关不起作用。
设置计分电路。每组在开始时预置成6分，抢答后主持人计分，答对一次加1分。(The design can accommodate a the Entrants digital intellectual Responder, each set answer in a key circuit has a first answer in the signal to identify and latch functions. Host to the system reset and sent the answer in instruction, participants answer in key, the group of the group light and display the answer in the group. At this point, the circuit has a self-locking function does not work in other groups to answer switch. Set Scoring circuit. Preset six points each at the beginning of the answer in scoring after the host, answer time, add 1 point.)
- 2012-06-10 12:58:44下载
- 积分：1
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FPGA中实现的硬件UDP 协议
FPGA中实现的硬件UDP 协议 FPGA中实现的硬件UDP 协议
- 2022-03-23 19:25:50下载
- 积分：1
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二进制除法器，采用移位相减的方法实现，位数可调
二进制除法器，采用移位相减的方法实现，位数可调-The source code of a divider
- 2023-08-14 00:00:02下载
- 积分：1
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FPGA
基于FPGA设计ADC0809采样控制器原代码-FPGA-based design ADC0809 Sampling Controller source
- 2022-05-30 01:45:47下载
- 积分：1
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oc_i2c_master_top_v92
I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
- 2009-10-10 10:43:18下载
- 积分：1
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MRAM2012
STT-MRAM磁性存储器全部verilog代码和仿真验证代码，包括行为模块，读写模块和控制模块，已经经过验证完全正确(STT-MRAM magnetic memory all the code and simulation code, including behavior module, reader module and the control module, has been proven entirely correct)
- 2020-06-29 14:20:02下载
- 积分：1
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基于VHDL的LED显示控制程序
常用的VHDL语言编写的LED灯控制程序,这是教学用的，开发板采用的是EPM240T100C5N，买开发板时附带的程序
- 2022-05-19 04:48:48下载
- 积分：1
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yuanchengxu
基于Verilog HDL的通信系统设计(Design of communication system based on Verilog HDL)
- 2011-11-19 13:36:54下载
- 积分：1
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4bit-adder_verilog
4位全加法器的modelsim工程带testbench(Four full-adder modelsim project with testbench)
- 2020-08-16 16:38:25下载
- 积分：1
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MAX531串行DA芯片的VHDL驱动，我应经在实际工程中试验过！
MAX531串行DA芯片的VHDL驱动，我应经在实际工程中试验过！-MAX531 serial DA chip VHDL driver, I shall be in the actual project tested!
- 2022-02-05 14:43:19下载
- 积分：1
