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Counter1s
counter number one to nine after 1s
- 2014-10-22 15:54:51下载
- 积分：1
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apb_uart
说明： 这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)
- 2021-04-12 14:18:57下载
- 积分：1
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cm03pr2
In computer storage, multipath I/O is a fault-tolerance and performance enhancement technique whereby there is more than one physical path between the CPU in a computer system and its mass storage devices through the buses, controllers, switches, and bridge devices connecting them
- 2013-06-09 00:41:09下载
- 积分：1
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主要是通过Altera公司的Cuclone系列的FPGA
主要是通过Altera公司的Cuclone系列的FPGA-EP1C3T144C8产生余弦波的源代码 基于LPM-ROM余弦波一周期含有256个10位数据；-Mainly through Altera s Cuclone series of FPGA-EP1C3T144C8 cosine wave generated source code based on the LPM-ROM cosine wave of one cycle containing 256 10-bit data
- 2023-06-17 01:00:03下载
- 积分：1
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Block-cipher-lock
密码锁verilog源代码，包括四个七段数码管显示模块，设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)
- 2014-01-11 23:57:19下载
- 积分：1
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wallace multiplier trees for 4:2
- 2022-02-10 01:12:10下载
- 积分：1
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apb2ahb
verilog code for apb to ahb convert
- 2021-01-05 03:38:55下载
- 积分：1
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这是可编程逻辑器件（CPLD）初学者的入门级文章，仅供参考。...
这是可编程逻辑器件（CPLD）初学者的入门级文章，仅供参考。-This is the programmable logic device (CPLD), the entry-level beginners articles for reference purposes only.
- 2022-01-22 10:28:59下载
- 积分：1
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master and slave code
集成电路的规模日益扩大
- 2022-03-02 13:07:25下载
- 积分：1
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median
说明： 用verilog编辑的中值滤波器！语言旁表有注释方便理解！(Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!)
- 2008-11-03 09:21:18下载
- 积分：1
