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Modulation
产生长度为100的随机二进制序列
发送载波频率为10倍比特率，画出过采样率为100倍符号率的BPSK调制波形（前10个比特） ，及其功率谱
相干解调时假设收发频率相位相同，画出x(t) 的波形，假设低通滤波器的冲激响应为连续10个1（其余为0），或连续12个1 （其余为0） ，分别画出两种滤波器下的y(t)，及判决输出（前10个比特）
接收载波频率为10.05倍比特率，初相位相同，画出x(t) 的波形，假设低通滤波器的冲激响应为连续10个1，画出两种滤波器下的y(t)，及判决输出（前20个比特）
采用DPSK及延时差分相干解调，载波频率为10倍比特率，画出a, b, c, d点的波形（前10个比特）
DPSK及延时差分相干解调，载波频率为10.25倍比特率时，画出a, b, c, d点的波形（前10个比特）
DPSK及延时差分相干解调，载波频率为10.5倍比特率时，画出a, b, c, d点的波形（前10个比特）
(Produce random binary sequence of length 100
The transmission carrier frequency is 10 times the bit rate, draw a sampling rate of 100 times the symbol rate of the BPSK modulation waveform (first 10 bits), its power spectrum
Coherent demodulation of assuming the same as the phase of the transmitting and receiving frequencies, and draw the waveform x (t), assuming that the impulse response of the low pass filter 10 consecutive 1 (the remainder is 0), or 12 consecutive 1 (the remainder is 0), y (t) is drawn under the two filters respectively, and the decision output (10 bits)
The received carrier frequency is 10.05 times the bit rate, the same initial phase, draw the waveform x (t), assuming that the impulse response of the low pass filter of 10 consecutive 1, shown under two filter y (t), and decision output (20 bits)
DPSK and delay differential coherent demodulation, the carrier frequency is 10 times the bit rate, draw a, b, c, d point of the waveform (first 10 bits)
DPSK and delay)
- 2020-12-14 08:19:14下载
- 积分：1
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grlib-gpl-1.1.0-b4108
gaisler公司在2011年发布的的leon3的源代码！(source code of leon3 )
- 2012-05-12 00:12:20下载
- 积分：1
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Design-of-taxi-meter-Based-on-FPGA
本文分析了当前国内外出租车计费系统的基本组成和工作原理及主要的两种设计方式:基于单片机的设计方式和基于FPGA的设计方式；并对这两种实现方式的优点和缺点进行分析，比较后确定本系统的方案：基于FPGA的出租车计费系统的设计。(This paper analyzes the current taxi charging system at home and abroad, working principle and basic components of two major design approach: the design methods based on single chip FPGA-based design approach and the two implementations to analyze the strengths and weaknesses, After comparing the program to determine the system: FPGA-based taxi billing system.)
- 2011-05-11 15:38:37下载
- 积分：1
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practica1
binary comparator with register
- 2012-04-24 17:39:04下载
- 积分：1
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DE0_Nano_SOPC_DEMO
Altera DE0-Nano 开发平台SOPC可编程片上系统实现官方Demo。(Altera DE0-Nano development platform the SOPC programmable on-chip system Official Demo.)
- 2013-03-18 06:16:13下载
- 积分：1
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用VHDL写的源代码程序，包涵三人表决器，七人表决器，全加器以及模24，模60的计数器，都是单文件的，由于程序小又多，所以集中在一起，供新学习VHDL语言的朋友...
用VHDL写的源代码程序，包涵三人表决器，七人表决器，全加器以及模24，模60的计数器，都是单文件的，由于程序小又多，所以集中在一起，供新学习VHDL语言的朋友们参考。-With VHDL source code written procedures, includes three of the voting machine, vote on seven people, and full adder, as well as modulus 24, modulus 60 counters, are single-file, as many small procedures, so together for the new Learning VHDL Language Reference friends.
- 2022-02-02 08:32:12下载
- 积分：1
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VHDL Storage/counter design
vhdl寄存/计数器设计-VHDL Storage/counter design
- 2022-01-26 02:37:06下载
- 积分：1
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VHDL 算术逻辑单元ALU_复旦
我是复旦的研究生。这是用VHDL写的ALU，仿真通过，压缩包里包括了每个源代码，而且都有相应的testbench，你直接加入你的工程当中就可以进行验证。设计时。我使用Modelsim环境来编写的。
- 2023-06-11 02:05:03下载
- 积分：1
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基于FPGA的温度计源代码，VHLL语言
基于FPGA的温度计源代码，VHLL语言-Thermometer-based FPGA source code, VHLL language
- 2023-06-09 16:00:03下载
- 积分：1
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Verilog
这是个关于verilog入门的文档，有同志对verilog感兴趣，可以下载此文档，以供参考。(This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.)
- 2011-11-06 13:18:07下载
- 积分：1
