-
TS_CHANNEL_656
利用ITU656接口传输数据流的方法!已得到应用!(ITU656 interface transfer data streams using the method! Has been applied!)
- 2010-02-23 14:16:18下载
- 积分:1
-
mp3_player
Altera board
Mp3 project
- 2011-12-27 15:04:02下载
- 积分:1
-
three_motor
matlab仿真MATLAB电机仿真精华50例--源代码异步电机\asymotor_stator.mdl
- 2010-01-16 22:02:43下载
- 积分:1
-
DDS now to the use of more extensive relative bandwidth, frequency conversion ti...
DDS在现在运用月来越广泛,在相对带宽、频率转换时间、相位连续性、正交输出、高分辨力以及集成化等方面都远远超过了传统频率合成技术所能达到的水平,为系统提供了优于模拟信号源的性能。利用DDS技术可以很方便地实现多种信号。在FPGA上实现的DDS-DDS now to the use of more extensive relative bandwidth, frequency conversion time, phase continuity, quadrature output, high-resolution and integration, and other aspects far more than the traditional frequency synthesizer technology can achieve the level To provide a superior analog signal source performance. DDS technology can be used very easily to a variety of signal. FPGA Implementation of DDS
- 2022-02-12 02:47:38下载
- 积分:1
-
DE2_115_CAMERA
实现DE2_115开发板上配套的500万像素cmos摄像头捕捉到的画面显示在VGA上(DE2_115 development board supporting 5,000,000 pixels cmos camera to capture the screen display in VGA)
- 2020-07-09 19:08:55下载
- 积分:1
-
vhdl 中各种数据类型的转换实现,可以调用函数库实现
vhdl 中各种数据类型的转换实现,可以调用函数库实现-date type change
- 2022-03-18 06:02:30下载
- 积分:1
-
Coding Style
良好的Coding Style能减少Bug,减少锁存器出现的可能以及其他隐藏逻辑错误,也有助于减小芯片面积或所用资源(Good Coding Style can reduce Bug, reduce the possibility of latches and other hidden logic errors, and also help to reduce chip area or resources used.)
- 2020-06-17 12:00:01下载
- 积分:1
-
AXI总线接口控制代码
本代码为简单AXI接口控制模块,具备数据的读写等传输功能,对总线传输学习者来说是很好的学习资料,可在此代码基础上进行更复杂功能接口的模块的开发。
- 2022-08-15 09:53:12下载
- 积分:1
-
TMS320DM642
学习DM642的开发板,适合DSP和pcb的初学者,容易上手(Learning DM642 development board)
- 2011-04-24 18:54:04下载
- 积分:1
-
VMD642_CPLD
本例程位于 VMD642_CPLD目录中。
使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使
用 Verilog HDL书写,编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)
- 2013-09-13 13:59:52下载
- 积分:1