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24小时计时时钟
实现24小时计时,因为位数不够,这里是12进位,可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分:1
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基于Xilinx fpga的ddr2 控制器设计方法
基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2
- 2022-08-11 18:36:22下载
- 积分:1
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RS编码在FPGA上实现的理论和方法,对设计RS编码很有帮助,且FOGA资源占有少...
RS编码在FPGA上实现的理论和方法,对设计RS编码很有帮助,且FOGA资源占有少-RS coding in the FPGA to achieve the theory and method useful for design RS encoding, and possession of less FOGA resources
- 2022-05-07 12:16:18下载
- 积分:1
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IIR
使用verilog语言描述的二阶巴特沃斯IIR滤波器,程序中有参数说明,已经运行通过(Using verilog language to describe the second-order Butterworth IIR filter, the program has parameter description has been run through)
- 2013-06-18 16:30:35下载
- 积分:1
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simwindfarm-v1.0
GFHGFHGFH DFHFDHD GHDHFDHHFD DFHFDHDF
- 2021-04-11 22:08:57下载
- 积分:1
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PCI arbitor VHDL
PCI Arbitor by VHDL -PCI Arbitor by VHDL
- 2022-03-18 15:09:07下载
- 积分:1
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vhdl的仿真
quartus 2的flv视频
vhdl的仿真
quartus 2的flv视频
-VHDL simulation of the flv video quartus 2
- 2022-04-12 23:18:28下载
- 积分:1
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proj-ASC
simple microprocessor that gives the greatest common divisor of 2 (4bit) numbers
- 2014-11-05 06:32:53下载
- 积分:1
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Modelsim concise user manual is very suitable for novice to use
Modelsim简明使用手册,十分适合新手使用-Modelsim concise user manual is very suitable for novice to use
- 2022-06-17 19:46:19下载
- 积分:1
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Verilog-learning-experience
初学学习verilog的经验,可以帮助新手以正确的思维方式,学习方法学习。(Verilog learning experience)
- 2013-09-30 09:51:04下载
- 积分:1