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uart代码
uart 串口 verilog 含testbench quartus工程 全双工 发送模块 接受模块
- 2022-04-07 03:03:29下载
- 积分：1
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fir_verilog_matlab
本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。(This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design results.)
- 2014-03-21 09:58:41下载
- 积分：1
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rfid new code
In the data management system a significant role of the Data link layer is to convert the unreliable physical link between reader and tag into a reliable link. Therefore, the RFID system employs the Cyclic Redundancy Check (CRC) as an error detection scheme. In addition for reader to communicate with the multiple tags, an anti-collision technique is required. The technique is to coordinate the communication between the reader and the tags. The common deterministic anti-collision techniques are based on the Tree algorithm such as the Binary Tree and the Query Tree algorithms.
- 2019-04-30 16:54:27下载
- 积分：1
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fpga_ofdm
这是篇<基于FPGA 的OFDM 宽带数据通信同步系统设计与实现>, 觉得甚是有用，大家共同学学。(This is the article <FPGA-OFDM-based broadband data communication systems design and implementation of synchronous> that even be useful, we all learn together.)
- 2007-06-13 00:02:43下载
- 积分：1
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PCI_arbi
PCI arbi verilog source code
- 2009-03-29 18:04:41下载
- 积分：1
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full adder
说明： vhdl code for full adder
- 2020-06-30 22:46:55下载
- 积分：1
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1K SRAM独立的读写端口，Verilog代码的ASIC设计
1K SRAM，安排字的32位，独立的读写端口，ASIC设计Verilog代码 采用偶校验对1的计数。 还带有测试平台
- 2022-02-07 13:55:18下载
- 积分：1
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ViterbiAlg
说明： Viterbi译码,IS-95中的1/2码率的卷积码(Viterbi decoding, IS-95 of 1/2 the rate Convolutional Codes)
- 2006-04-11 14:10:58下载
- 积分：1
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shi01
FPGA上机文件一所以在FPGA中采用同 步设计非常重要 MAX+PLUS II可以计算出数据传输需要(fpga Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency)
- 2017-10-24 16:41:14下载
- 积分：1
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apb_uart_sv-pulpinov1
SystemVerilog 写的APB总线接口的uart 代码，带testbench.(Uart code of APB bus interface written by SystemVerilog, with testbench.)
- 2018-04-17 14:44:15下载
- 积分：1
