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lecg_局部增强的时钟门控
这是一个关于的RTL时钟门控技术LECG此源代码是在门控时钟的应用LECG技术
- 2022-03-02 23:58:15下载
- 积分:1
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防盗灯verilog
利用XC9572-PQ44(Xilinx CPLD)制作的一款家用防盗报警器的Verilog源代码及原理图,当房门打开后,15秒内若没有按下Key1,则会自动拨打设定手机号(当然,要另连接一台手机)
- 2022-01-26 14:59:55下载
- 积分:1
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ArhivaAdrian
Anticipated Adder for Xilinx
- 2011-11-15 06:57:02下载
- 积分:1
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verilog语言的fpga全数字锁相环ADPLL程序
应用背景ADPLL数字锁相环在fpga上工程中有广泛的应用,程序有verilog语言编写关键技术全数字锁相环ADPLL由verilog HDL语言编写在FPGA上使用。
- 2022-02-12 07:22:59下载
- 积分:1
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maichongceliang
对于已获得的脉冲包络采样序列,需测量的脉冲特征参数主要有:脉冲幅值(PA)、脉冲到达时间(TOA)和脉冲宽度(PW)。实际测量中,脉冲波形的形状是各种各样的,但其主要的参数有脉冲幅度、脉冲宽度、脉冲周期、脉冲占空比、脉冲前沿(上升时间)、脉冲后沿(下降时间)、脉冲上冲、脉冲下冲、脉冲下垂、脉冲顶部不平度等,脉冲参数的计量主要就是对这些参数进行计量。本程序包实现基于FPGA实现脉冲宽度和重复周期的测量。(Who have access to the pulse envelope sample sequence, the pulse measurement to be the main characteristic parameters are: pulse amplitude (PA), pulse time of arrival (TOA) and pulse width (PW). The actual measurement, the pulse shape is a wide variety of shapes, but its main parameters of the pulse amplitude, pulse width, pulse period, pulse duty cycle, pulse leading edge (rise time), pulse along (down time), the red pulse, pulse undershoot, pulse droop, pulse irregularities, such as at the top, the measurement of pulse parameters is mainly the measurement of these parameters. The package FPGA-based pulse width and repetition to achieve the measurement cycle.)
- 2009-07-08 14:32:08下载
- 积分:1
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LCD1602
通过编写verilog语言完成数据的在液晶LCD1602显示(By writing verilog language to complete the data displayed on the LCD LCD1602)
- 2013-08-04 13:12:05下载
- 积分:1
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fht_latest.tar
FAST HADAMARD TRANSFORM VERILOG FOR IMAGE PROCESSING
- 2013-08-19 13:47:40下载
- 积分:1
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can_exm1_sys
CAN总线的数据采集,FPGA到USB。verilog hdl语言。(CAN bus data acquisition, FPGA to the USB. verilog hdl language.)
- 2013-05-31 15:01:11下载
- 积分:1
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Center
使用Xilinx3S400开发的钢板检测算法中心化算法,通过测试。(a vhdl-program use Xilinx3S400)
- 2009-04-12 22:09:45下载
- 积分:1
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BGM benchmark
// DEFINES
`define BITS 32 // Bit width of the operands
`define NumPath 34
module bgm(clock,
reset,
sigma_a,
sigma_b,
sigma_c,
Fn,
dw_x,
dw_y,
dw_z,
dt,
Fn_out
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input [`BITS-1:0] sigma_a;
input [`BITS-1:0] sigma_b;
input [`BITS-1:0] sigma_c;
input [`BITS-1:0] Fn;
input [`BITS-1:0] dw_x;
input [`BITS-1:0] dw_y;
input [`BITS-1:0] dw_z;
input [`BITS-1:0] dt;
- 2022-04-09 23:29:23下载
- 积分:1