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FPGA秒表

于 2023-01-19 发布 文件大小:1.41 MB
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下载积分: 2 下载次数: 1

代码说明:

基于 Xilinx Spartan 6 的、在七段译码管上显示、用按键控制计时开始、结束、逐秒累加功能的verilog代码,同时它是此开发板的一个demo工程,也是中山大学移动信息工程课程作业项目之一。希望对有需要参考的孩子有所帮助

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