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FPGA_CPLD-SHC
FPGA_CPLD-SHC多款FPGA CPLD开发板的原理图，很好的线路设计参考(FPGA_CPLD-SHC Variety of FPGA CPLD development board schematics, a good reference circuit design)
- 2013-03-04 23:36:01下载
- 积分：1
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master and slave code
集成电路的规模日益扩大
- 2022-03-02 13:07:25下载
- 积分：1
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NAND型闪存接口程序 NANDflash
NAND型闪存接口程序 里面包含了datasheet以及测试程序 (NAND flash memory interface program)
- 2020-06-26 00:00:02下载
- 积分：1
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LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
- 2013-07-25 14:43:43下载
- 积分：1
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navigation
Ship navigation project
- 2014-12-04 18:58:16下载
- 积分：1
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256字节深度的RS232串口程序,共分4个模块,顶层文件FIFO程序串口收和串口发.经过测试已用于产品.可靠!...
256字节深度的RS232串口程序,共分4个模块,顶层文件FIFO程序串口收和串口发.经过测试已用于产品.可靠!-Depth of 256-byte Serial RS232 procedures, divided into four modules, top-level document procedures FIFO serial and serial-fat collection. After the test has been used in products. Reliable!
- 2022-01-26 06:37:51下载
- 积分：1
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ecc
说明： This paper analyzes the cryptography scheme of the Trust Platform Model(TPM). The focus of the discussion would be the comparison of elliptic curve cryptography and the nowadays widely used 2048-bit RSA in evaluating which would be better suited to be used on TPM. A TPM implementation scheme based on ECC is proposed, which includes encryption and decryption schemes, signature and verification scheme, key agreement scheme. Corresponding examples of TPM commands would also be given.
- 2019-06-13 14:53:45下载
- 积分：1
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within waveform generator, Adder, classic dual
内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
- 2023-09-02 09:40:03下载
- 积分：1
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CODE_VHDL_INITIALIZING 液晶电视 DISPLAY(KHỞI TẠO HIỂN THỊ LCD)
CODE_VHDL_INITIALIZING 液晶电视 DISPLAY(KHỞI TẠO HIỂN THỊ LCD)
- 2022-03-17 18:12:45下载
- 积分：1
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VHDL
A Full adder using half adder unit in vhdl
- 2010-01-05 11:39:14下载
- 积分：1
