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Verilog--image-sample
基于Verilog的图像采集、处理和存储程序,初学者参考,高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)
- 2021-04-16 11:48:54下载
- 积分:1
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VHDLFIFO
用Verilog 写一个8x16 的FIFO,完成先入先出的功能,并且在FIFO读空时输出EMPTY
有效信号,读指针RP 不再移动;FIFO 写满时输出FULL 有效信号,并且即使WR 有效也
不再向存储单元中写入数据(写指针WP 不再移动)。
(NO)
- 2020-09-20 20:17:51下载
- 积分:1
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This tutorial presents some basic concepts that can be helpful in debugging of a...
This tutorial presents some basic concepts that can be helpful in debugging of application programs written in the Nios II assembly language, which run on Altera’s DE2 boards.
- 2022-08-19 12:45:10下载
- 积分:1
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pe1lca
vhdl code for programming
- 2012-11-22 21:37:52下载
- 积分:1
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VHDL写的PWM发生器,仿真通过,波形基本完美,可以用于直流电机的控制...
VHDL写的PWM发生器,仿真通过,波形基本完美,可以用于直流电机的控制-PWM generator written in VHDL, simulation is passed, the basic waveform perfect, can be used for DC motor control
- 2022-09-19 14:15:03下载
- 积分:1
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编译实现循环码的产生,用FOR循环分别对其中的码元进行设置。...
编译实现循环码的产生,用FOR循环分别对其中的码元进行设置。-Implementation cycle of the compiler generated code, respectively, using FOR Cycle one of the key element of the set.
- 2022-08-11 07:55:45下载
- 积分:1
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Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.
描述了使用FPGA接口PDIUSBD12开发USB接口的流程.-Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.
- 2023-04-29 07:25:03下载
- 积分:1
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FFT_64
64点FFT设计,基于FPGA频域的设计PPT,基4算法(64 point FFT design, based on FPGA frequency domain design, PPT, base 4 algorithm)
- 2021-01-14 16:08:48下载
- 积分:1
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24_Timer
说明: 使用Verilog编写的24位定时器,具有apb 总线接口,可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
- 2021-04-27 21:38:44下载
- 积分:1
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用max+plusII编写的vhdl程序
乒乓球游戏机
用max+plusII编写的vhdl程序
乒乓球游戏机-with max plusII vhdl procedures for the preparation of the table tennis game
- 2022-03-04 06:41:57下载
- 积分:1