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在USB contreoller CRC5块
crc5 bolck in usb contreoller
- 2022-03-06 23:01:25下载
- 积分：1
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四位除法器的VHDL源程序
四位除法器的VHDL源程序-four division of VHDL source
- 2022-01-27 20:04:11下载
- 积分：1
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自己今年的毕业设计DDS波形发生器,有正弦波,方波,三角波,锯齿波....
自己今年的毕业设计DDS波形发生器,有正弦波,方波,三角波,锯齿波.-Their own design this year
- 2022-03-07 14:56:41下载
- 积分：1
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1
verilog 典型电路设计包含各种常用电路的源码和详细的解释，适合新手使用(Verilog typical circuit design includes a variety of commonly used circuit source code and detailed explanations, suitable for beginners to use
)
- 2014-03-19 10:48:41下载
- 积分：1
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uart_tr(3)
uart_tr 异步串口通信主机 使用verilog HDL语言编写(uart_tr the host of the uart )
- 2015-06-08 21:02:17下载
- 积分：1
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tAtan2Cordic
是codic算法实现atan的C程序，包括定点和浮点程序，已经通过验证。(Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.)
- 2021-02-04 09:59:58下载
- 积分：1
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AXI4_Sim
说明： 实现AXI,AXI-Lite乒乓地址的传输，AXI,AXI-Lite已经封装成内核，可直接修改后使用(Realize the transmission of table tennis address of Axi and Axi Lite. Axi and Axi Lite have been encapsulated into a kernel, which can be directly modified and used)
- 2020-05-31 15:20:16下载
- 积分：1
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NAND_flash_verilog_vhdl
很好的NAND Flash 硬件驱动语言，支持VHDL和verilog 语言方便移植，如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。(NAND Flash Controller Reference
This reference design is used to interface a NAND Flash device and provides a simple host end interface. The host
end interface of this design is user-configurable. It provides buffer select signal, buffer write enable signal, address
bus, data bus, error status signal, control and handshake signals for the user......)
- 2021-03-08 22:59:28下载
- 积分：1
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JTAG
边界扫描技术相关资料，含各个模块的介绍。很有参考价值。(JTAG TAG CONTROLLER)
- 2016-02-24 19:10:03下载
- 积分：1
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DDS
文利用直接数字频率合成器(DDS)与CPLD技术和单片机控制技术，研制和
设计了高分辨率、高稳定度的函数信号发生(Wen using direct digital frequency synthesizer (DDS) and CPLD technology and single-chip microcomputer control technology, development and
Design of high resolution, high stability function of the signal
)
- 2013-08-27 14:20:22下载
- 积分：1
