-
jiaotongdeng
交通灯控制系统VHDL源码，用VHDL语言、MAXPLUS2环境设计实现(VHDL core)
- 2009-03-05 20:01:07下载
- 积分：1
-
C6747_test
tms320c6747的测试程序 。用于dsp各个模块的测试，很好的例子(dsp tms320c6747)
- 2015-01-18 15:20:33下载
- 积分：1
-
usbd_ucos
基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)
- 2020-09-09 09:38:02下载
- 积分：1
-
gps
基于fpga和dsp架构的gps接收机的设计和实现(Design and Implementation of gps Receiver Based on fpga)
- 2017-05-25 17:44:51下载
- 积分：1
-
系统介绍EDA技术的发展概述，相关概念，VHDL语言、MAX+PULS、QUARTUS的设计方法。...
系统介绍EDA技术的发展概述，相关概念，VHDL语言、MAX+PULS、QUARTUS的设计方法。-System overview of the development of EDA technology, related concepts, VHDL language, MAX+ PULS, QUARTUS design method.
- 2022-07-09 22:03:23下载
- 积分：1
-
the transmitter and receiver modules for serial communication
the transmitter and receiver modules for serial communication
- 2022-07-22 02:02:39下载
- 积分：1
-
du to fpga 4*4 keyscan verilog
基于fpga的4*4键盘扫描verilog程序-du to fpga 4*4 keyscan verilog
- 2022-01-25 20:49:28下载
- 积分：1
-
altera de2 sd 卡源程序。调试成功的
altera de2 sd 卡源程序。调试成功的-altera de2 sd card source. Debugging success
- 2022-06-20 23:18:53下载
- 积分：1
-
Cadence-Allegro-PCB-SI
利用Cadence Allegro PCB SI进行SI仿真分析(Performed using the Cadence Allegro PCB SI SI simulation analysis)
- 2013-08-06 22:17:46下载
- 积分：1
-
the program have designed a PCM signal timing modules, including the CLK input,...
该程序设计了一个产生PCM码流时序信号的模块，他包括输入端CLK，SET及输出端Q1,Q2,Q3-the program have designed a PCM signal timing modules, including the CLK input, and output SET Q1, Q2 and Q3
- 2022-02-15 04:03:30下载
- 积分：1
