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Data Encryption Standard or DES
加密已经成为我们生活的一部分,我们
- 2022-04-28 04:42:22下载
- 积分:1
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BulkIn是FPGA向CY7C68013发送数据
BulkOut是FPGA从CY7C68013接收数据,可以用LED显示...
BulkIn是FPGA向CY7C68013发送数据
BulkOut是FPGA从CY7C68013接收数据,可以用LED显示
-BulkIn is the FPGA to the CY7C68013 is BulkOut send data CY7C68013 receive data from the FPGA, you can use LED display
- 2022-08-15 04:42:44下载
- 积分:1
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SimpleSpi
master spi的源代码(verilog),包括文档,测试程序(master spi the source code (verilog), including documentation, testing procedures)
- 2007-01-29 21:03:51下载
- 积分:1
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Fractional_Time_Delay
Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.
- 2020-12-16 22:29:12下载
- 积分:1
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FPGA控制AD7321的模块
FPGA控制AD7321的模块,是本人亲自试验过的。有Verilog源码,和简单文档(Fpga control module of ad 7321, is I personally tested. Verilog source code, and simple documentation)
- 2018-01-31 20:04:27下载
- 积分:1
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ps2接口的工程实现,顶层为原理图,便于理解
ps2接口的工程实现,顶层为原理图,便于理解-ps2 interface engineering implementation, the top-level schematic diagram for easy understanding of
- 2022-07-10 06:48:35下载
- 积分:1
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基于VHDL语言的并串转换程序,有四位的并行输出转换为串行输出...
基于VHDL语言的并串转换程序,有四位的并行输出转换为串行输出-Based on the VHDL language and string conversion process, there are four parallel output is converted to serial output
- 2023-03-31 21:30:04下载
- 积分:1
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CORDIC 代码
Xilinx CORDIC 算法 MATLAB Verilog仿真(arctan.m Kn.m sin_cos.m MATLAB Verilog)
- 2019-03-27 09:53:35下载
- 积分:1
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CPU
C++获取CPU占用率,一个类和一个头文件(Gets the CPU Use rate)
- 2015-01-23 11:15:32下载
- 积分:1
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saa7113_vhdl-config
saa7113_配置.SAA7113视频解码系列芯片的一种,8位彩色配置(saa7113_ configuration. SAA7113 video decoder chips in an 8-bit color configuration)
- 2013-11-26 08:57:58下载
- 积分:1