登录
首页 » Verilog » 一种新型设计的可逆 2:4 译码器

一种新型设计的可逆 2:4 译码器

于 2023-03-10 发布 文件大小:4.47 kB
0 86
下载积分: 2 下载次数: 1

代码说明:

可逆的逻辑已收到

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • ahdl--sine-wave-code-with-rom-look-up-table_imp
    hi this is an verilog codes
    2011-11-11 14:30:21下载
    积分:1
  • rfid_re
    VHDL实现 DDS。大家共享吧,一起学习,一起进步(VHDL realize DDS. U.S. to share it with learning, with progress)
    2008-05-16 15:12:13下载
    积分:1
  • UART
    说明:  串口通信vivado实现,带有仿真文件,可实现数据收发(the uart program based on vivado)
    2020-07-02 16:15:57下载
    积分:1
  • 74HC161
    74ls161 基于verilog语言的实现 源程序在压缩包的hdl文件夹中(74ls161 language based on the realization of verilog source package in compressed folder hdl)
    2020-07-01 17:00:01下载
    积分:1
  • My-Simple-Specturm--Analyzer
    基于LabVIEW FPGA的频谱估计与分析(the power spectrum estimation and analysis based on LabVIEW FPGA)
    2013-11-13 08:45:40下载
    积分:1
  • VHDLaVerilogcomplie(20151022105744)
    一个关于VERILOG与VHDL混合编程,混合验证的资料(A hybrid programming on VERILOG and VHDL, mixed verification data)
    2015-12-14 17:19:26下载
    积分:1
  • electricwatch
    用VHDL语言设计多功能的电子表。实现基本电子表的时间显示、闹钟、秒表等功能(VHDL language design with multi-functional electronic watch. The time table to achieve basic electronic display, alarm clock, stopwatch functions)
    2010-05-07 17:11:53下载
    积分:1
  • m_ca7
    verilog编写的基于CA算法的m序列发生器,其中验证了多种CA系数来实现m序列。(CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.)
    2011-10-26 14:33:59下载
    积分:1
  • test1
    利用matlab,对偏振控制器进行仿真,最终在邦加球上进行显示(Using matlab, simulation of the polarization controller eventually be displayed on the Poincare Sphere)
    2013-04-07 10:42:15下载
    积分:1
  • dac
    简易函数发生器,能产生正弦波,三角波,梯形波,方波,并且可调频率和幅度值。(Simple function generator can produce sine, triangle wave, trapezoidal wave, square wave, and the adjustable frequency and amplitude values.)
    2011-08-28 14:11:37下载
    积分:1
  • 696518资源总数
  • 105949会员总数
  • 22今日下载