-
VGA
说明: 用VERILOG编写的一个可以实现VGA显示的程序.....(Prepared using a VERILOG VGA display program can .....)
- 2011-03-04 12:25:21下载
- 积分:1
-
四VHDL模块的家庭,已经过测试,在ISE8.1通过
四位全家器的VHDL语言模块,已经在ISE8.1上经过测试通过-family of four VHDL modules, has been tested on ISE8.1 through
- 2022-03-21 16:25:17下载
- 积分:1
-
total
一个简单的后台模板,主要为贵金属直播室有喊单等功能类型的。
ps:由于涉及到iframe本地跨域问题,因此查看时请在服务器上进行审阅。(A simple background template, mainly for the precious metal living room, such as the type of function.
PS: as a result of the local cross domain problem involved in the iframe, so check it out on the server.)
- 2015-11-18 09:00:49下载
- 积分:1
-
wola
WOLA polyphase filter加权跌接累加FFT信道化技术(WOLA polyphase filter bank)
- 2020-09-28 14:57:45下载
- 积分:1
-
Verilog
用Verilog实现一个基于Mesh拓扑结构的路由器网络(Using Verilog to implement a router network based on Mesh topology)
- 2021-03-25 15:49:14下载
- 积分:1
-
IIC主设备的代码实现(verilog),从设备模型
IIC主设备的代码实现(verilog),从设备模型-IIC main equipment of the code (verilog), from the device model
- 2022-09-07 15:50:02下载
- 积分:1
-
用VHDL和verilog实现的四人抢答器
用VHDL和verilog实现的四人抢答器-using VHDL and verilog realization of four Responder
- 2023-07-17 00:15:04下载
- 积分:1
-
a
说明: 用verilog实现除法器,调用了ip核,不仅有源代码,还有测试程序的时序编写(verilog ise divider)
- 2013-07-21 15:03:31下载
- 积分:1
-
彩条产生程序 color_bar
说明: 彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)
- 2020-06-22 06:20:01下载
- 积分:1
-
Timing1111_Symcronization
使用Verilog编写的时间同步模块,解决位同步问题,ISE12.2下编译通过(Time synchronization module written in Verilog, bit synchronization issues under ISE12.2 compiled by)
- 2021-05-07 14:28:36下载
- 积分:1