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vhdl实现的鼠标协议，代码可读性高，适合作为参考案例。
vhdl实现的鼠标协议，代码可读性高，适合作为参考案例。-VHDL realize mouse agreement, the code readable, suitable as a reference case.
- 2022-02-06 08:18:06下载
- 积分：1
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人脸识别（3D）
基于高清视频的3D人脸识别源代码，四万多行，经过FPGA实际验证，最近调试完毕。(The source code of 3D face recognition based on HD video, more than 40,000 lines, has been verified by the actual FPGA, and has been debugged recently.)
- 2019-07-01 16:22:46下载
- 积分：1
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串口程序，基于VHDL 的，很好的程序
快下吧
串口程序，基于VHDL 的，很好的程序
快下吧-Serial procedures, based on VHDL, and a very good program, are you fast
- 2022-02-04 10:08:53下载
- 积分：1
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国外的VHDL应用例子，大家可一好好参考一下！
国外的VHDL应用例子，大家可一好好参考一下！-abroad VHDL Application examples, we can make reference to a properly!
- 2022-01-25 20:56:43下载
- 积分：1
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eetop.cn_Uvm_spi_bl_reg_tb
uvm apb verification env
- 2020-08-11 16:48:27下载
- 积分：1
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以太网总线源代码，里面有详细的文档说明，已经过FPGA验证。...
以太网总线源代码，里面有详细的文档说明，已经过FPGA验证。-Ethernet bus source code, which has a detailed document that has been FPGA verification.
- 2023-08-25 00:30:05下载
- 积分：1
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The document may download to FPGA chip to complete the clock divider,serial
本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
- 2022-09-03 00:05:03下载
- 积分：1
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dct_verilog
用FPGA实现dct变换。verilog语言实现，在quartus9.0中验证，含整个工程(dct transform verilog language in quartus9.0 verify, with the entire project)
- 2020-12-02 18:59:24下载
- 积分：1
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clo
实现时分秒的计数和校正实现时分秒的计数和校正(Realized and correction of minutes and seconds count)
- 2009-12-21 22:52:39下载
- 积分：1
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Combined unit GPS clock synchronization detection unit merger GPS synchronized c...
合并单元内GPS同步时钟的检测
合并单元内GPS同步时钟的检测-Combined unit GPS clock synchronization detection unit merger GPS synchronized clock detection
- 2023-05-04 14:30:04下载
- 积分：1
