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vhdl_lms
vhdl 语言实现的lms算法的自适应滤波器 两种实现方式 包括改进(VHDL language lms algorithm adaptive filter implemented in two ways including improved)
- 2012-04-26 18:15:02下载
- 积分：1
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dds32_1
说明： 频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)
- 2011-04-14 13:45:22下载
- 积分：1
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emmc
emmc协议的实现代码，包含了SD协议，usb实现协议(The implementation code of EMMC protocol)
- 2021-04-08 16:39:00下载
- 积分：1
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关于FPGA的书籍，介绍了大量的Verilog实例，对初学者很有帮助
关于FPGA的书籍，介绍了大量的Verilog实例，对初学者很有帮助-Books on the FPGA, introduced a large number of Verilog examples very helpful for beginners
- 2022-11-11 12:40:04下载
- 积分：1
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This is an FPGA
这个是一个基于FPGA的SDRAM控制器系统，实现对SDRAM的读写操作，用来实现时序的控制-This is an FPGA-based SDRAM controller system, the read and write operations to SDRAM to achieve the control of timing
- 2022-02-02 20:49:24下载
- 积分：1
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gtx
说明： ip core of the transceiver gtx
- 2019-04-02 00:10:03下载
- 积分：1
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chuankou
本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分：1
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fpga-jpeg
包含DCT变换，RGB2YCBCR,JPEG等多个verilog代码及工程(Contains DCT transform, RGB2YCBCR, JPEG and many other verilog code and project)
- 2013-07-02 14:10:16下载
- 积分：1
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callback
This is code of UVM CALLBACK function.
- 2020-06-24 15:40:02下载
- 积分：1
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aFifo
verylog语言编程，为异步flipflop的程序。具有数据传输功能，数据位数可以用户设定(verylog language programming for asynchronous Flipflop procedures. With a data transmission function, data can be user set the median)
- 2007-08-28 10:26:03下载
- 积分：1
