登录
首页 » VHDL » 本教程介绍了如何与IO设备在DE2板和H.

本教程介绍了如何与IO设备在DE2板和H.

于 2022-01-31 发布 文件大小:163.00 kB
0 147
下载积分: 2 下载次数: 1

代码说明:

This tutorial explains how to communicate with IO devices on the DE2 Board and how to deal with interrupts using C and the Altera Monitor Program. Two example programs are given that diplay the state of the toggle switches on the red LEDs. The fi rst program uses the programmed I/O approach and the second program uses interrupts.-This tutorial explains how to communicate with IO devices on the DE2 Board and how to deal with interrupts using C and the Altera Monitor Program. Two example programs are given that diplay the state of the toggle switches on the red LEDs. The fi rst program uses the programmed I/O approach and the second program uses interrupts.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • zhuangtai
    状态机的典型饮用,可供学习模仿之用,四个状态,简单易学(State machine of the typical drinking, can be used to learn to imitate, four state, easy to learn)
    2007-11-11 21:36:15下载
    积分:1
  • 1
    说明:  matlab code for JTAG cable checking
    2014-02-04 19:27:39下载
    积分:1
  • An SRAM of the source program, it is the SRAM 256kbx16bit
    一个sram的源码程序,它是256kbx16bit的sram-An SRAM of the source program, it is the SRAM 256kbx16bit
    2022-05-27 20:08:48下载
    积分:1
  • JTAG
    边界扫描技术相关资料,含各个模块的介绍。很有参考价值。(JTAG TAG CONTROLLER)
    2016-02-24 19:10:03下载
    积分:1
  • verilogexample
    verilog学习资料。附带简单的源代码列子,可以直接使用和仿真。(verilog learning materials. Source code with a simple Lie Zi, and simulation can be used directly.)
    2011-05-26 11:53:24下载
    积分:1
  • Cordic_matlab
    实现自然对数运算的cordic算法的matlab浮点仿真,以及针对FPGA硬件平台的定点仿真测试(Achieve natural logarithm of cordic algorithm matlab floating point emulation, and FPGA hardware platform for fixed-point simulation testing)
    2013-11-01 15:10:09下载
    积分:1
  • frame_syn
    2010-04-28 10:34:32下载
    积分:1
  • 非常好的VHDL音乐
    library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity song is    port(clk_4MHz,clk_4Hz:in std_logic;      ----预置计数器和乐谱产生器的时钟         digit:buffer std_logic_vector(6 downto 0);  ----高、中、低音数码管指示         zero:out std_logic_vector(4 downto 0);     ----用于数码管高位置低  
    2022-12-29 04:50:03下载
    积分:1
  • HuaWeiVerilog
    主要用来介绍如何编写高质量的verilog程序的(Is mainly used to describes how to write high-quality verilog programs)
    2020-09-18 09:07:55下载
    积分:1
  • S03_基于ZYNQ的DMA与VDMA的应用开发
    VIVADO dma以及vdma 使用文档 基于ZYNQ 7020(vivado DMA&VDMA example text of zynq)
    2020-06-17 11:40:02下载
    积分:1
  • 696516资源总数
  • 106415会员总数
  • 3今日下载