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clock
软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 多功能数字钟(Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock)
- 2009-03-22 12:44:34下载
- 积分：1
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cyc2_cii5v1
这是1C6开发板上元件的具体资料。此开发板有掉电不丢失程序的功能，就是靠着几个芯片(development board components specific information. This development board is not lost restart procedures, it was relying on a few chips)
- 2007-02-15 10:22:14下载
- 积分：1
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Crack_QII72_FULL_License
Quartus II 7.2最完美的license破解器!(Quartus II 7.2 FULL and perfect License!)
- 2012-03-09 11:15:22下载
- 积分：1
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uart
用Verilog HDL，实现的FPGA串口调试程序，已经在硬件上调试成功(With Verilog HDL, FPGA serial debugger implemented in hardware debugging has been successful)
- 2015-07-23 15:24:12下载
- 积分：1
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AMI1
本代码是用VERILOG语言描述的AMI码的解码的程序，经过调试是正确的。代码简单易懂。(This code is described in VERILOG language AMI code decoding process, after debugging is correct. Code is easy to understand.)
- 2021-04-22 14:48:48下载
- 积分：1
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03b1730cb31f464fa006a05ce501e8f18dc0
BIOMETRIC VICE RECOGNITION
- 2017-12-11 19:27:51下载
- 积分：1
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实战训练21 SDRAM硬件控制
说明： SDRAM硬件控制,fpga的verilog语言，适合学习(SDRAM hardware control, Verilog language of FPGA, suitable for learning)
- 2020-04-29 11:45:16下载
- 积分：1
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一个16位cpu的vhdl代码。具体内容我也不清楚，自己慢慢研究吧...
一个16位cpu的vhdl代码。具体内容我也不清楚，自己慢慢研究吧-a 16 cpu of VHDL code. Specific content is not clear to me that their study it slowly
- 2022-01-26 05:10:10下载
- 积分：1
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ALTERA Cyclone1C20 Nios开发板，protel99格式
ALTERA Cyclone1C20 Nios开发板，protel99格式-ALTERA Cyclone1C20 Nios，protel99
- 2022-01-23 10:08:20下载
- 积分：1
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asynchronous serial communication port of the FPGA, function (1) serial data rec...
异步串口通信口在FPGA实现，功能有（1）串行数据接收的同步控制；（2） 串行数据发送的同步控制-asynchronous serial communication port of the FPGA, function (1) serial data receiver synchronization control; (2) the transmission of serial data synchronization control
- 2023-06-21 16:25:03下载
- 积分：1
