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  1. 编程语言:VHDL
  2. 代码类别:其他
  3. 发布时间:不限
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1. ALU_74181_me

  学习ALU的设计方法。 2、用HDL语言采用行为描述的方法完成74181的逻辑设计 。(Learn the design method of ALU. 2, use HDL language to use behavioral description method to complete 74181 logical design.)

0
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78
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2020-11-11发布

2. Lpfilter_20190503

说明:  环路滤波器是通信信号调制解调中最重要的一个部分,环路滤波器设计的好坏将直接影响到接收机的性能指标,二阶锁频辅助三阶锁相环路滤波器可以稳定跟踪具有加加速度的信号源,是现代通信中非常实用的技术,本文中详细编写了单载波信号产生模块、信道噪声模块、数字正交下变频模块、鉴频鉴相模块、环路滤波器模块,并包含了完整的testbench模块,对于初学者非常有用。(Loop filter is the most important part of communication signal modulation and demodulation. The design of loop filter will directly affect the performance index of receiver. The second-order frequency locking assisted third-order phase-locked loop filter can stably track the signal source with acceleration speed, which is a very practical technology in modern communication. In this paper, the single carrier signal generation module and channel noise are written in detail Sound module, digital orthogonal down conversion module, frequency and phase detection module, loop filter module, and contains a complete testbench module, which is very useful for beginners.)

3
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176
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2020-11-11发布

3. verilog

说明:  i2c module,有i2c主机和从机模块(i2c module verilog VHDL base on i2c protocol)

1
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97
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2020-10-26发布

4. Muliplexer

说明:  Multiplexer 4 to 1 on Modelsim

1
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102
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2020-10-14发布

5. singlecycle_mips

  single cycle mips design by verilog.

50
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105
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2020-09-07发布

6. OFDM_618

说明:  基于FPGA的OFDM同步,包含时钟模块、ROM读取模块、峰值检测模块、帧同步模块(OFDM synchronization based on FPGA includes clock module, Rom reading module, peak detection module and frame synchronization module)

2
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87
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2020-08-12发布

7. FPGA数字信号处理实现原理及方法代码

说明:  本光盘是《数字信号处理FPGA实现》一书的配书光盘,内容包括了书中第二章给出的所有示例以及该书的12个实验完整的工程文件。 本光盘根目录下有3个文件夹,分别为dsp48_application,dsp48e_application和DSP_Example。(This CD-ROM is the CD-ROM of the book "FPGA implementation of digital signal processing". It includes all the examples given in Chapter 2 and the complete engineering documents of 12 experiments in the book. There are three folders in the root directory of this CD-ROM, which are dsp48_ application,dsp48e_ Application and DSP_ Example.)

2
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88
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2020-08-01发布

8. 千年工具大全

说明:  千年服务端修改工具,千年db数据在线修改(Millennium server modification tool Millennium server modification tool)

19
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124
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2020-07-07发布

9. LnE

  verilog写的LnE算法,可用于计算指数和对数(Verilog written in LnE algorithm, can be used to calculate the index and the logarithm)

12
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77
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2020-06-30发布

10. VHDL

  带有异步清零、异步置位功能的边沿JK触发器(With asynchronous reset, asynchronous setting function of edge JK flip-flop)

1
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99
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2020-06-30发布

11. 第七次课--视频图像DCT处理及水印嵌入

  熟悉IIC协议总线协议,采用IIC总线对图像采集传感器寄存器进行配置,并转换为RGB565格式。 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。 利用 SDRAM 接口模块的设计,实现了刷新、读写等操作;为提高SDRAM 的读写带宽,均采用突发连续读写数据方式;并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。 利用双线性插值方法实现对图像640×480到1024×768的放大操作。 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format. Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface. With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA. The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768. Complete the VGA display interface design.)

1
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92
浏览
2020-06-25发布

12. 第七次课--视频图像DCT处理及水印嵌入_2

说明:  熟悉IIC协议总线协议,采用IIC总线对图像采集传感器寄存器进行配置,并转换为RGB565格式。 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。 利用 SDRAM 接口模块的设计,实现了刷新、读写等操作;为提高SDRAM 的读写带宽,均采用突发连续读写数据方式;并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。 利用双线性插值方法实现对图像640×480到1024×768的放大操作。 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format. Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface. With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA. The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768. Complete the VGA display interface design.)

6
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60
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2020-06-25发布

13. Altium Partner SN-1000010 r10

  Browser modularization processing, browser modularization combing, browser modularization expansion

0
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72
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2020-06-24发布

14. Altium Partner SN-1000010 r10

说明:  Browser modularization processing, browser modularization combing, browser modularization expansion

1
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81
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2020-06-24发布

15. 等精度测频??

  等精度测频法,有需要的可以下载看看哟,word中包含的代码(Equal Precision Frequency Measurement Method)

0
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80
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2020-06-22发布

16. 等精度测频??

说明:  等精度测频法,有需要的可以下载看看哟,word中包含的代码(Equal Precision Frequency Measurement Method)

1
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59
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2020-06-22发布

17. Copy

  this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

0
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101
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2020-06-21发布

18. Copy

说明:  this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

1
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66
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2020-06-21发布

19. bianyuanjiance

  图像采集 VGA输出 图像的边缘 ov7670(V image acquisition VGA output image edge)

0
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73
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2020-06-21发布

20. bianyuanjiance

说明:  图像采集 VGA输出 图像的边缘 ov7670(V image acquisition VGA output image edge)

2
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67
浏览
2020-06-21发布