-
学习使用HDL Bencher生成测试积累，并直接调用ModelSim进行仿真的方法....
学习使用HDL Bencher生成测试积累，并直接调用ModelSim进行仿真的方法.-learning HDL Bencher generate test accumulation, and called directly ModelSim simulation methods.
- 2022-02-28 22:36:00下载
- 积分：1
-
keyscan
用verilog语言写的简单的键盘扫描代码，适合初学者，用alter的软件编写的程序代码。(Using verilog language to write simple keyboard scan code, suitable for beginners, with alter software program written code.)
- 2013-09-13 22:59:11下载
- 积分：1
-
ideal_6pulse
理想三相转单相 基于 spwm 的逆变器，可调(Ideal three-phase switch to a single the phase based spwm inverter)
- 2012-11-04 21:15:32下载
- 积分：1
-
使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。
使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
- 2022-12-07 20:00:03下载
- 积分：1
-
SHIFT_8REG是8位的一个具有移位功能的寄存器，每一次数据打入都会从这个寄存器的最低位打入，并相应进行向左移位。
ODD_110BREG是一个3位的备...
SHIFT_8REG是8位的一个具有移位功能的寄存器，每一次数据打入都会从这个寄存器的最低位打入，并相应进行向左移位。
ODD_110BREG是一个3位的备份寄存器，寄存器中存放的是奇数帧的同步头，也就是110。
EVEN_9BHREG是一个8位的备份寄存器，寄存器中存放的是偶数帧的同步头，也就是10011011。这两个寄存器的初始值在系统一开始就打入。
-SHIFT_8REG is eight with a displacement of the functional Register, Each will enter the data from the register into the lowest point, and the left shift accordingly. ODD_110BREG is a three backup Register, the Register is stored in the odd frame synchronization head, is 110. EVEN_9BHREG 8 is a backup Register, which register is kept even the first frame synchronization, is 10011011. This register the two initial value of the system into a start.
- 2022-05-15 03:11:22下载
- 积分：1
-
1024-point-FFT-in-verilog.pdf
1024 点得快速傅里叶变换算法 FPGA in verilog(1024 point FFT on a FPGA written in verilog)
- 2014-03-26 22:56:23下载
- 积分：1
-
phone
用DE0开发板实现电话计费器，基本功能：可设置通话模式，能初始化话费余额，拨动开关可进入通话模式，并根据通话时间和相应通话模式扣除相应的费用。通话过程中能够通过开关切换显示通话时间和话费余额，并可暂停通话。压缩包里有详细的WORD文档的说明，包括波形仿真和DE0的引脚功能介绍。(Implemented by DE0 board telephone billing, basic function: to set the call mode, you can initiate credit balance, toggle switch into the talk mode, and deduct the cost of a call based on call time and the corresponding mode. Call talk time and can be displayed by switching credit balance, and mute. Compression bag has a detailed description of WORD documents, including the waveform simulation and DE0 pin function description.)
- 2020-11-06 13:19:49下载
- 积分：1
-
数控分频器设计:对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。计数器溢出时，输出‘1’电平，同时溢出时的‘1’电平反馈给计数器的输入端...
数控分频器设计:对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。计数器溢出时，输出‘1’电平，同时溢出时的‘1’电平反馈给计数器的输入端作为装载信号；否则输出‘0’电平。
-NC divider design : an adder counter, loading the initial count value, have different frequency output signal of the overflow. Counter overflow, the output"1 "Level, Overflow at the same time the"1 "level feedback to the counter input signal as loading; Otherwise output"0 "level.
- 2022-04-28 17:05:55下载
- 积分：1
-
用于FPGA的反量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。...
用于FPGA的反量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA used to quantify anti-HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
- 2022-04-08 04:33:51下载
- 积分：1
-
LDPC.DIFFERENT-CODE-LONGTH
LDPC码不同码长对比。码率选择1/2.码长分别为256，512，1024.(LDPC codes of different code length contrast. Bitrate select 1/2 yards long were 256,512,1024.)
- 2012-11-22 10:53:04下载
- 积分：1
