登录
首页 » VHDL » 1、 利用FLEX10的片内RAM资源,根据DDS原理,设计产生正弦信号的各功能模块和顶层原理图; 2、 利用实验板上的TLC7259转换器,将1中得到的正弦信...

1、 利用FLEX10的片内RAM资源,根据DDS原理,设计产生正弦信号的各功能模块和顶层原理图; 2、 利用实验板上的TLC7259转换器,将1中得到的正弦信...

于 2022-01-25 发布 文件大小:21.67 kB
0 134
下载积分: 2 下载次数: 1

代码说明:

1、 利用FLEX10的片内RAM资源,根据DDS原理,设计产生正弦信号的各功能模块和顶层原理图; 2、 利用实验板上的TLC7259转换器,将1中得到的正弦信号,通过D/A转换,通过ME5534滤波后在示波器上观察; 3、 输出波形要求: 在输入时钟频率为16KHz时,输出正弦波分辨率达到1Hz; 在输入时钟频率为4MHz时,输出正弦波分辨率达到256Hz; 4、 通过RS232C通信,实现FPGA和PC机之间串行通信,从而实现用PC机改变频率控制字,实现对输出正弦波频率的控制。-a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • EX7_BINARY2GRAY
    本模块是实现格雷码和二进制码的转换,并给出仿真测试文件(This module is to achieve the conversion of Gray code and binary code, and give the simulation test file)
    2015-04-14 16:48:38下载
    积分:1
  • 数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;...
    数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;
    2023-07-21 04:20:04下载
    积分:1
  • PID_Verilog
    说明:  PID算法用verilog语言实现,实测可用,由三个模块组成(The PID algorithm is implemented in Verilog language. The actual measurement is available. It consists of three modules.)
    2019-04-30 02:32:21下载
    积分:1
  • Rotating coordinates high
    高速计算机旋转坐标算法的硬件实现,用于快速傅里叶算法的核心单元-Rotating coordinates high-speed computer hardware algorithm for fast Fourier algorithm is the core unit
    2022-02-16 05:47:02下载
    积分:1
  • tdma_code
    tdma参数化模块。可以自动生成2的n次的tdma哥时隙,用户可根据需要自己配置参数(tdma see the number of model lumps. 2 n basis following manner tdma chance possible 以自 dynamic generation, for root needed self-placement see number)
    2013-09-03 21:52:51下载
    积分:1
  • 波特率选择VHDL源代码没有错误调试
    波特率可供选择的vhdl源程序,已调试无错误-Baud rate options VHDL source code has no error debug
    2022-04-25 04:22:33下载
    积分:1
  • Lab15_sw2reg
    开关数据加载到寄存器并显示的设计与实现.3. 设计一个可以把4个开关的内容存储到一个4位寄存器的电路,并在最右边的7段显示管上显示这个寄存器中的十六进制数字。我们使用到去抖动模块clock_pulse, 用btn[0]作为输入;8位寄存器模块,用btn[1]作为加载信号;7段显示管上的显示模块x7segbc;分频模块clkdiv,用以产生模块clock_pulse和x7segbc的clk190时钟信号。(Design of switching data is loaded into the register and display the.3. design and implementation of a 4 switch content storage circuit to a 4 bit register, and in the 7 section of the most on the right shows the register in the sixteen decimal digital display tube. We used to go to the jitter module clock_pulse, with btn[0] as the input 8 bit register module, as the loading signal by btn[1] 7 segment display module on the x7segbc pipe frequency module clkdiv, clk190 clock signal for generating module clock_pulse and x7segbc.)
    2014-03-30 09:50:48下载
    积分:1
  • 7 digital display decoder design 7 Digital is pure combinational circuits, usual...
    7段数码显示译码器设计7段数码是纯组合电路,通常的小规模专用IC,如74或4000系列的器件只能作十进制BCD码译码,然而数字系统中的数据处理和运算都是二进制的,所以输出表达都是十六进制的,为了满足十六进制数的译码显示,最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器,输出信号LED7S的7位分别接数码管的7个段,高位在左,低位在右。例如当LED7S输出为“1101101”时,数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1;接有高电平的段发亮,于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
    2022-08-11 21:55:01下载
    积分:1
  • 乘法器,实现了乘法和除法的功能,能够进行32位的运算
    乘法器,实现了乘法和除法的功能,能够进行32位的运算-Multiplier to achieve the functions of multiplication and division to carry out 32-bit computing
    2022-03-24 02:44:07下载
    积分:1
  • i2c ADT75温度传感器
    I2C温度传感器ADT75的控制源码 使用verilog 状态机实现 易入门-I2C for ADT75 temperature sensor
    2022-02-14 14:53:33下载
    积分:1
  • 696518资源总数
  • 106161会员总数
  • 5今日下载