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基于basys3的推箱子游戏
基于FPGA的游戏实例,开发板为Xilinx的basys3,VGA显示(Basys3, VGA Display of Xilinx Development Board Based on Game Example of FPGA)
- 2021-03-12 13:09:25下载
- 积分:1
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dp_xiliux 的 CPLD Verilog设计实验,流水灯演示.代码测试通过.
dp_xiliux 的 CPLD Verilog设计实验,流水灯演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, water lamp demonstration. code test.
- 2023-08-11 06:35:04下载
- 积分:1
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四位静态数码管控制器,含详细的中文注释,VERILOT源码....
四位静态数码管控制器,含详细的中文注释,VERILOT源码.-4 static digital tube controller, with detailed notes in Chinese, VERILOT source.
- 2022-03-29 22:12:43下载
- 积分:1
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uart-for-fpga
说明: Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA.
Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit!
The UART controller was simulated and tested in hardware.
- 2020-06-24 22:00:02下载
- 积分:1
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6713emiftofpgatopci,这个是完整的一套从6713的emif到fpga的双口ram,然后主机通过9054到双口ram,交换数据完成
6713emiftofpgatopci,这个是完整的一套从6713的emif到fpga的双口ram,然后主机通过9054到双口ram,交换数据完成-6713emiftofpgatopci, this is a complete set of the EMIF from 6713 to the FPGA
- 2022-01-25 23:08:47下载
- 积分:1
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dlx.tar
these is about code for dlx processor
- 2010-03-15 17:52:53下载
- 积分:1
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xc2s100E FPGA的原理图
给想涉足FPGA的新人参考
xc2s100E FPGA的原理图
给想涉足FPGA的新人参考-xc2s100E FPGA schematic diagram of the FPGA would like to set foot in the new reference
- 2023-05-12 14:50:04下载
- 积分:1
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这是个vhdl编写的16bit的加减法器
这是个vhdl编写的16bit的加减法器-This is vhdl prepared by the modified instruments used in the 16bit
- 2022-02-15 07:17:54下载
- 积分:1
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用VHDL编写的FIR数字滤波器的程序可以用在FPGA工作。
FIR数字滤波器程序,采用vhdl编写,可用于FPGA电路-FIR digital filter procedure for the preparation of VHDL can be used in FPGA circuit
- 2022-08-15 20:37:14下载
- 积分:1
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RISC
说明: URISC的RTL级设计,Verilog代码(Design: URISC RTL Verilog)
- 2019-06-16 23:07:39下载
- 积分:1